United Electronic Industries DNR-AI-207 User Manual Download Page 1

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DNx-AI-207

—

User Manual

16-Channel, 18-bit, Sequential Sampling, Differential

Analog Input Board with Cold-Junction Compensation

for the PowerDNA Cube and RACK Series Chassis

December 2017

PN Man-DNx-AI-207

Summary of Contents for DNR-AI-207

Page 1: ...it Sequential Sampling Differential Analog Input Board with Cold Junction Compensation for the PowerDNA Cube and RACK Series Chassis December 2017 PN Man DNx AI 207 Copyright 1998 2017 United Electron...

Page 2: ...68 2350 Also see the FAQs and online Live Help feature on our web site Internet Support Support support ueidaq com Website www ueidaq com FTP Site ftp ftp ueidaq com Product Disclaimer WARNING DO NOT...

Page 3: ...nout 9 1 7 1 Analog Input Ground Connections 10 1 8 Data Representation 11 1 8 1 CJC Data 11 Chapter 2 Programming with the High Level API 12 2 1 About the High level Framework 12 2 2 Creating a Sessi...

Page 4: ...cember 2017 www ueidaq com 508 921 4600 Copyright 2017 United Electronic Industries Inc 3 4 5 Setting the Scan Rate 19 3 4 6 Reading Data Timestamps 19 3 5 Programming Scan Rate 21 3 6 Configuring Cha...

Page 5: ...600 Copyright 2017 United Electronic Industries Inc Table of Figures Chapter 1 Introduction 1 1 1 Block Diagram of DNx AI 207 I O Board 5 1 2 Photo of DNA AI 207 Analog Input Board 8 1 3 Pinout of the...

Page 6: ...n of this Manual This AI 207 User Manual is organized as follows Introduction Chapter 1 provides an overview of DNx AI 207 features device architecture connectivity and logic Programming with the High...

Page 7: ...instance it can represent a command as in the following example You can instruct users how to run setup using a command such as setup exe Bold typeface will also represent field or button names as in...

Page 8: ...eading from the built in CJC sensor on UEI s DNA STP AI U or AI 207TC terminal panels When used with DNA STP AI U or 207TC panel the DNx AI 207 also features a direct connection to thermocouples with...

Page 9: ...us 1 single ended dedicated CJC channel Programmable DIO line 1 external trigger ADC resolution 18 bits Sampling rate 1 S s 16 kS s per channel 16 kS s max aggregate for entire board FIFO size 512 sam...

Page 10: ...el switching settling time delays and the conversion process Also it reads data from the converter at the maximum possible rate and sends it over the isolation barrier to the non isolated logic for th...

Page 11: ...Section 1 5 3 for more information about autozero functionality The number of input channels passing through the input multiplexer will affect the maximum allowable sample rate per channel For example...

Page 12: ...nel multiplexer This scheduling will lower the maximum sample rate of channels 1 5 4 Oversampling Engine Another feature the oversampling engine permits the DNx AI 207 to acquire as many samples as po...

Page 13: ...lustrated in Figure 1 2 Figure 1 2 Photo of DNA AI 207 Analog Input Board Table 1 3 AI 207 Indicators LED Name Description RDY Indicates board is powered up and operational STS Indicates which mode th...

Page 14: ...6 AIN2 AIN4 33 15 AIN3 AIN5 32 14 AIN4 CJC 31 13 AIN5 AIN6 30 12 AIN6 AIN7 29 11 AIN7 AIN8 28 10 AIN8 AIN9 27 9 AIN9 AIN10 26 8 AGND AIN11 25 7 AIN10 AIN12 24 6 AIN11 AIN13 23 5 AIN12 13V 50mA 22 4 AI...

Page 15: ...e signal source and eliminate the resistors shown in Figure 1 4 for floating differential input signals Input Configuration Type of Input d e d n u o r G g n i t a o l F Typical Signal Sources Thermoc...

Page 16: ...fer is filled with its relative position number If you read sequential data it could mean the ADC failed to start To convert data into floating point use the following formula 1 8 1 CJC Data Raw CJC V...

Page 17: ...he concept is the same no matter which programming language you use Please refer to the UeiDaq Framework User Manual for more information on use of other programming languages 2 2 Creating a Session T...

Page 18: ...re a temperature between 0 0 and 1000 0 degrees C from type J thermocouples scale temperatures in Celsius degrees and using CJC built in compensation from the STP AI U in differential mode session Cre...

Page 19: ...nfigureTimingForSimpleIO 2 6 Reading Data Reading data from the AI 207 is done using a reader object There is a reader object to read raw data coming straight from the A D converter There is also a re...

Page 20: ...The Framework extends the low level API with additional functionality that makes programming easier and faster For additional information regarding low level programming refer to the PowerDNA API Refe...

Page 21: ...z rtDMAP VMAP Designed for closed loop control applications Users set up a map of I O boards and channels from which to acquire data Input data is stored in I O board FIFOs at a rate paced by its hard...

Page 22: ...hold the channel list and sets channels 0 through CHAN_LIST_SZ 1 to be configured with a gain of 1 and set to differential mode for i 0 i CHAN_LIST_SZ i cl i i DQ_LNCL_GAIN DQ_AI208_GAIN_1 DQ_LNCL_DI...

Page 23: ...a Note that the final two parameters would be pointers to arrays to hold acquired data but in this first read that data is disregarded The DqAdv207Read function returns status flags one of which indic...

Page 24: ...n rate in immediate mode i e to 100 Hz in this example you can use the following API Program the scan clock aka CL clock to acquire 100 0 scan s The function DqCmdSetClock can program clocks on severa...

Page 25: ...rt the CJC temperature reading to the correct temperature scale and then convert the acquired channel data to the thermocouple temperature Note that thermocouple constants can be found in TCConversion...

Page 26: ...st to control the sampling of each channel through the mux The CV clocks also called conversion clocks are typically referred to with simultaneously sampled I O boards For the AI 207 you will use the...

Page 27: ...selects the internal channel list clock cl source as a time base To select a clock generated external to the board and routed in over the chassis SYNC bus for example a 1PPS synchronized clock gen era...

Page 28: ...rames frames in the buffer uint32 ppevent packets per DQ_ePacketDone event uint32 mode mode of operations Single Cycle Recycled error handling uint32 dirflags transfer direction and additional flags u...

Page 29: ...in connector scheme The DNA STP 37 is connected to the I O board via either DNA CBL 37 or DNA CBL 37S series cables The dimensions of the STP 37 board are 4 2w x 2 8d x1 0h inch or 10 6 x 7 1 x 7 6 cm...

Page 30: ...24 CAUTION 2 CJC Sensor 5 Cleaning up 14 Configuring Excitation 12 Configuring the Timing 13 14 Connectors 9 Conventions 2 Creating a Session 12 D Data Representation 11 F Features 4 G Ground Connecti...

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