United Electronic Industries DN-SL-514 Series User Manual Download

Page: 32 / 33

DNx-SL-514 Synchronous Serial Interface Board

Appendix A

May 2018

www.ueidaq.com



508.921.4600



United Electronic Industries, Inc.

Appendix

A.1 Accessories

The following cables and STP boards are available for the SL-514 board.

DNA-CBL-37

3ft, 37-way flat ribbon cable; connects SL-514 to panels to DNA-STP-37.

DNA-CBL-37S

3ft, 37-way shielded cable; connects SL-514 to panels to DNA-STP-37.

DNA-STP-37

37-way screw terminal panel.

DNA-STP-37D

37-way direct-connect screw terminal panel.

JP2

— 20-position

terminal block

CABLE SHIELD

JP3

— 20-position

terminal block

N/C

JP1

—

DB-37 (male)

37-pin connector

UP+1

20 1

UP+1

21 2

UP+1

22 3

UP+1

23 4

UP+1

24 5

UP+1

25 6

UP+1

26 7

UP+1

27 8

UP+1

28 9

UP+1

29 10

UP+1

30 11

UP+1

31 12

UP+1

32 13

UP+1

33 14

UP+1

34 15

UP+1

35 16

UP+1

36 17

UP+1

37 18

UP+1

JP3

Summary of Contents for DN-SL-514 Series

Page 1: ...anual Synchronous Serial Interface Board with Differential Inputs Outputs for the PowerDNA Cube and RACK Series Chassis May 2018 PN Man DNx SL 514 Copyright 1998 2018 United Electronic Industries Inc All rights reserved ...

Page 2: ...668 2350 Also see the FAQs and online Live Help feature on our web site Internet Support Support support ueidaq com Website www ueidaq com FTP Site ftp ftp ueidaq com Product Disclaimer WARNING DO NOT USE PRODUCTS SOLD BY UNITED ELECTRONIC INDUSTRIES INC AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS Products sold by United Electronic Industries Inc are not authorized for use as critica...

Page 3: ...tatus Reporting 11 1 7 5 Termination 11 1 7 6 Electrical Specification for Serial Port Lines 11 1 8 Wiring Connectors pinout 12 Chapter 2 Programming with the High Level API 13 2 1 About the High level Framework 13 2 2 Creating a Session 13 2 3 Configuring the Resource String 14 2 4 Configuring an SSI Master Port 14 2 5 Configuring an SSI Slave Port 15 2 6 Configuring Minimum Pulse Widths 16 2 7 C...

Page 4: ... 514 Synchronous Serial Interface Board ii Table of Contents May 2018 www ueidaq com 508 921 4600 Copyright 2018 United Electronic Industries Inc 3 3 5 Reading Received Master Data 25 3 3 6 Reading Status 25 ...

Page 5: ... United Electronic Industries Inc List of Figures Chapter 1 Introduction1 1 1 Photo of DNA SL 514 Synchronous Serial Board 6 1 2 Block Diagram of SL 514 7 1 3 SSI Transmission Waveform 8 1 4 Example of Debouncing and Tv time Delays 9 1 5 Settable Termination Circuit Diagram 11 1 6 Pinout Diagram of the SL 514 Board 12 ...

Page 6: ...ganization of this Manual This SL 514 User Manual is organized as follows Introduction Chapter 1 provides an overview of DNx SL 514 features device architecture connectivity and logic Programming with the High Level API Chapter 2 provides an overview of the how to create a session configure the session and interpret results with the high level framework API Programming with the Low Level API Chapt...

Page 7: ...atim For instance it can represent a command as in the following example You can instruct users how to run setup using a command such as setup exe Bold typeface will also represent field or button names as in Click Scan Network Text formatted in fixed typeface generally represents source code or other text that should be entered verbatim into the source code initialization or other file Examples o...

Page 8: ...ial Interface The SL 514 offers four synchronous serial interface SSI channels Each SSI channel can be programmed independently and each SSI channel offers a master and slave port Each master or slave port can be enabled independently 1 2 2 Data Rates Supported data rates are between 300 bps to 1 3 Mbps programmed independently per channel The master output clock is generated with 0 1 or better ac...

Page 9: ...ifferential I O using at RS 422 RS 485 logic voltage levels Data rates programmable up to 1 3 Mbps Data word length programmable from 3 to 32 bits Master clock source is generated with 0 1 or better accuracy FIFO storage 2048x32 FIFO for master allowing 1024 data words along with 1024 timestamps and 1024x32 FIFO for slave with watermark Asynchronous event interrupt generated upon FIFO full Start s...

Page 10: ...rd Output 1024 word GENERAL SPECIFICATIONS Protection 7 kV ESD 350V isolation Input High Low voltage RS 422 485 compatible Output High Low voltage RS 422 485 compatible RS 422 485 termination resistors Software selectable Ȱ Electrical Isolation 350 Vrms chan chan and chan chassis Input output buffer chip LTC1687 or equivalent Power consumption 3W Operating range Tested 40 to 85 C Humidity range 0 ...

Page 11: ... in Table 1 2 and illustrated in Figure 1 1 Figure 1 1 Photo of DNA SL 514 Synchronous Serial Board Table 1 2 SL 514 Indicators LED Name Description RDY Indicates board is powered up and operational STS Indicates which mode the board is running in OFF Configuration mode e g configuring channels running in point by point mode ON Operation mode DB 37 female 37 pin I O connector RDY LED STS LED DNA b...

Page 12: ...differential CLOCKIN and DATAOUT pins 1 7 1 Master Slave Device Description The SL 514 master device generates an output clock CLKOUT at the user specified baud rate Data is received by the master device on DATAIN as most significant bit MSB first with no particular start or stop sequence required no start bit or stop bit The slave device receives an input clock on CLOCKIN The clock transition cau...

Page 13: ...s received by the master controller the master holds its clock high for the user programmed pause time tp When the full word is transmitted out of the slave device the slave holds its data low for a user programmable transfer timeout period tm which starts on the falling edge of the clock synchronized to the LSB of data After the tm period the slave drives its DataOut pin high The master controlle...

Page 14: ...edge of the clock after the LSB transmission and the falling edge of the first clock of the next data word refer to tp in Figure 1 3 The m_tp or s_tp parameter can be programmed a 32 bit number of 66 MHz clocks Tm time delay The transfer timeout delay also called the monoflop time represents the time delay between the DataOut pin driving low after the LSB is transmitted and the time the DataOut dr...

Page 15: ...em clock this will result in dividing down from 33 MHz If your application requires a baud rate that is not evenly divisible by 33 MHz the actual baud you will get is one that is as close as possible to your requested rate and evenly divisible by 33 MHz If your application requires finer granularity the PLL can be used 1 7 3 FIFO Operation Timestamping Data storage for each master controller is pr...

Page 16: ...watermark currently set to half the FIFO size SL514_CSTS_TXFHF Slave RX FIFO is above watermark currently set to half the FIFO size SL514_CSTS_RXFHF The SL 514 master controllers only store SSI words that are received without timing errors in the FIFO 1 7 5 Termination The SL 514 features termination resistors on both the receiver and transmitter lines to provide a driver load impedance of 100 Ω R...

Page 17: ... Board All signals are referenced relative to isolated ground iGND NOTE If you are using a accessory panel with the SL 514 please refer to the Appendix for a description of the panel M_CLKOUT0 1 M_DATAIN0 2 S_DATAOUT0 3 S_CLKIN0 4 GND 0 5 M_CLKOUT2 10 M_DATAIN2 11 S_DATAOUT2 12 S_CLKIN2 13 GND 2 14 M_CLKOUT3 15 M_DATAIN3 16 S_DATAOUT3 17 S_CLKIN3 18 Rsvd 19 20 M_CLKOUT0 21 M_DATAIN0 22 S_DATAOUT0 ...

Page 18: ...ng Data Section 2 10 Cleaning up the Session Section 2 11 2 1 About the High level Framework UeiDaq Framework is object oriented and its objects can be manipulated in the same manner from different development environments such as Visual C Visual Basic or LabVIEW UeiDaq Framework is bundled with examples for supported programming languages Examples are located under the UEI programs group in Start...

Page 19: ...onfigure one or more channel s as a master SSI port The following call configures SSI master ports 0 and 1 of a SL 514 set as device 1 It configures the following parameters Bits per second the number of bits per second transferred over the synchronous port unsigned integer Word size The number of bits per word 3 to 32 unsigned integer Clock Enable Enable or disable the clock output boolean Termin...

Page 20: ...eger Word size The number of bits per word 3 to 32 unsigned integer Transmit Enable Enable or disable the data output boolean Termination Enable Enable or disable termination resistor boolean Pause Time Specifies the time delay tp in microseconds between two consecutive clock sequences from the master double Transfer Timeout Specifies the minimum time tm in microseconds required by the slave to re...

Page 21: ...thod NOTE This value can be incremented in 15 ns steps and should be set to the smallest possible setting that solves an issue of signal ringing debounces the signal The following code reads the minimum pulse width parameters for the master port on channel 1 and the slave port on channel 2 The following code sets the minimum pulse width parameters for the master port on channel 1 to 50 ns and the ...

Page 22: ...ond it will return whatever number of bytes are available every second 2 8 Configuring Timestamps Users can check whether timestamping is enabled and optionally enable it on each received frame Timestamping can only be enabled on master ports Use the IsTimestampingEnabled method to check whether timestamping is enabled The method returns a boolean true or false Set the EnableTimestamping property ...

Page 23: ...list NOTE The number of bits written in the output word is programmed as Word size 3 32 bits in the CreateSSISlavePort API The following sample code shows how to create a writer object tied to port 0 ssi0 and send a frame of 128 data words to the SSI port 2 11 Cleaning up the Session The session object will clean itself up when it goes out of scope or when it is destroyed To reuse the object with ...

Page 24: ...ming easier and faster For additional information regarding low level programming refer to the PowerDNA API Reference Manual located in the following directories On Linux systems PowerDNA x y z docs On Windows systems Start All Programs UEI PowerDNA Documentation 3 2 Low level Functions Table 3 1 provides a summary of SL 514 specific functions All low level functions are described in detail in the...

Page 25: ...ocated in the following directories On Linux systems PowerDNA x y z src DAQLib_Samples On Windows Start All Programs UEI PowerDNA Examples Code examples specifically for the SL 514 have 514 specified in the name i e Sample514 c SL 514 can be operated using the immediate point to point data acquisition protocol Sample514 c provides an example of acquiring data using this mode DqAdv514Enable Enables...

Page 26: ...tion typedef struct uint32 ch_cfg channel configuration uint32 flags Reserved uint32 clk_source clock source for master uint32 baud_rate baud rate for master 100Hz to 1 3 MHz Master SSI setting sends clocks receives data uint32 m_word_sz master word size 3 to 32 bits uint32 m_debounce debouncing settings 0 bypass uint32 m_trigger Tx trigger source uint32 m_Tv Tv master uint32 m_Tp Tp master uint32...

Page 27: ...for baud L514CFG_CLK_BASE use system 66MHz clock and divide it L514CFG_CLK_PLL use on board PLL as a clock source baud_rate uint32 300 baud to 1 3 Megabaud uint32 m_word_sz master 3 to 32 bits in the word uint32 m_debounce master debouncing settings 0 bypass 1 thru 15 4 thru 18 15 ns clocks i e programming a 1 results in 4 15ns or 60 ns debouncing delay m_trigger master trigger source that allows ...

Page 28: ...aud Actual baud rate This function returns an actual_baud parameter To set the baud rate the user defined baudrate value is used to program the PLL The PLL dividers may not be able to produce the exact programmed rate in which case the value closest to the user programmed rate is used Users can check the actual_baud parameter to know what baud rate is used s_trigger slave trigger source that allow...

Page 29: ...o IOM received from DqOpenIOM int devn Board device inside the IOM chassis int channel_mask Bitmask of channels 1 to enable or keep running and 0 to disable As an example setting channel_mask 0x3 will enable channel 0 and channel 1 3 3 4 Writing Slave Data for Transmit Each slave port on the SL 514 has a 1024 FIFO for holding data to be output The FIFO can be filled using the DqAdv514WriteFIFO API...

Page 30: ...l programmed with this function chan Alternatively the DqAdv514Status API reads status conditions from all channels listed in a bitmask of channels Refer to Section 3 3 6 for more information about reading status and for a list of status conditions that can be read from channels 3 3 6 Reading Status The DqAdv514Status API is used to read channel status This API allows you to read status informatio...

Page 31: ...ion Description SL514_CSTS_TXERR 1L 19 Slave TX Timing Error 1 error detected master clock arrived too early sticky bit cleared after read SL514_CSTS_RXERR 1L 18 Master RX Timing Error 1 error detected slave drove RX data high during mono flop time sticky bit cleared after read SL514_CSTS_TXFE 1L 17 Slave TX FIFO is empty 1 FIFO empty sticky bit cleared after read SL514_CSTS_RXFF 1L 16 Master RX F...

Page 32: ...onnects SL 514 to panels to DNA STP 37 DNA STP 37 37 way screw terminal panel DNA STP 37D 37 way direct connect screw terminal panel to JP2 JP2 20 position terminal block 4 2 CABLE SHIELD JP3 20 position terminal block N C N C 24 22 20 JP1 DB 37 male 37 pin connector UP 1 20 1 UP 1 UP 1 21 2 UP 1 UP 1 22 3 UP 1 UP 1 23 4 UP 1 UP 1 24 5 UP 1 UP 1 25 6 UP 1 UP 1 26 7 UP 1 UP 1 27 8 UP 1 UP 1 28 9 UP...

Page 33: ...nchronous Serial Interface Board Index 28 Index B Block Diagram 7 C Cable s 27 Configuring the Resource String 13 Connectors and Wiring 12 Conventions 2 Creating a Session 13 H High Level API 13 J Jumper Settings 7 O Organization 1 S Screw Terminal Panels 27 Setting Operating Parameters 7 Specifications 5 Support ii Support email support ueidaq com ii Support FTP Site ftp ftp ueidaq com ii Support...

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