NINA-W1 series - System integration manual
UBX-17005730 - R15
System description
Page 9 of 54
C1 - Public
When using an LPO, also enable boot-time calibration by setting
CONFIG_ESP32_RTC_CLK_CAL_CYCLES
to at least 3000. The higher the number, the better accuracy, on the expense of boot time.
Frequency stability and system time accuracy is decreased when using sleep modes. To increase
accuracy, use an LPO and enable both high-resolution and RTC timers by setting
CONFIG_ESP32_TIME_SYSCALL
accordingly.
If the ULP (ultra-low-power) co-processor is not required, the ULP functionality can be disabled by
unsetting the
CONFIG_ESP32_ULP_COPROC_ENABLED
option.
If the LPO detection fails, increase the
CONFIG_ESP32_RTC_XTAL_CAL_RETRY
option.
If “
flash read err, 1000
” messages are printed to the console after deep sleep reset, increase the
CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY
value from its default 2000 µs
.
See the Espressif ESP32 SDK [8] for more information on how these, and additional configuration
options and API functions, affect power consumption, frequency stability, and boot-time behavior.
1.5
Supply interfaces
1.5.1
Module supply design (VCC)
NINA-W1 series modules include an integrated Linear Voltage converter that transforms the supply
voltage. The output of the converter, presented at the
VCC
pin, provides a stable system voltage.
1.5.2
Digital I/O interfaces reference voltage (VCC_IO)
NINA-W1 series modules include an additional voltage supply input for setting the I/O voltage level.
A separate
VCC_IO
pin enables module integration in many applications with different voltage supply
levels (1.8 V or 3.3 V for example) without level converters. NINA-W1 series modules currently support
3.3 V IO levels only.
1.5.3
VCC application circuits
The power for NINA-W1 series modules is applied through the VCC pins. These supplies are taken
from either of the following sources:
•
Switching Mode Power Supply (SMPS)
•
Low Drop Out (LDO) regulator
An SMPS is the ideal design choice when the available primary supply source is of a higher value than
the operating supply voltage of the module. This offers the best power efficiency for the application
design and minimizes the amount of current drawn from the main supply source.
⚠
When taking VCC supplies from an SMPS make sure that the AC ripple voltage is kept as low as
possible at the switching frequency. Design layouts should focus on minimizing the impact of any
high-frequency ringing.
Use an LDO linear regulator for primary VCC supplies that have a relatively low voltage. As LDO linear
regulators dissipate a considerable amount of energy, LDOs are not recommended for the step down
of high voltages.
DC/DC efficiency should be regarded as a trade-off between the active and idle duty cycles of an
application. Although some DC/DC devices achieve high efficiency at light loads, these efficiencies
typically degrade as soon as the idle current drops below a few milliamps. This can have a negative
impact on the life of the battery.
