EVA-7M - Hardware Integration Manual
UBX-12003235 - R05
Production Information
Design-in
Page 9 of 42
2.2
Interfaces
The EVA-7M provides UART, SPI and DDC (I
2
C compatible) interfaces for communication with a host CPU. A USB
interface is also available on dedicated pins (see section 2.2.4).
The UART, SPI and DDC pins are supplied by
VCC_IO
and operate at this voltage level.
Four dedicated pins can be configured as either 1 x UART and 1 x DDC or a single SPI interface selectable by
D_SEL
pin. Table 1 below provides the port mapping details.
Pin 32 (D_SEL) = “high” (left open)
Pin 32 (D_SEL) = “Low” (connected to GND)
UART TX
SPI MISO
UART RX
SPI MOSI
DDC SCL
SPI CLK
DDC SDA
SPI CS
Table 1: Communication Interfaces overview
It is not possible to use the SPI interface simultaneously with the DDC or UART interface.
For debugging purposes, it is recommended to have a second interface e.g. USB available that is
independent from the application and accessible via test-points.
For each interface, a dedicated pin can be defined to indicate that data is ready to be transmitted. The TX Ready
signal indicates that the receiver has data to transmit. A listener can wait on the TX Ready signal instead of
polling the DDC or SPI interfaces. The UBX-CFG-PRT message lets you configure the polarity and the number of
bytes in the buffer before the TX Ready signal goes active. The TX Ready function is disabled by default.
The TX Ready functionality can be enabled and configured by proper AT commands sent to the involved
u-blox wireless module supporting the feature. For more information see
GPS Implementation and
Aiding Features in u-blox wireless modules
The TX Ready feature is supported on version LEON FW 7.xx and LISA-U2 01S and above.
2.2.1
UART interface
A UART interface is available for serial communication to a host CPU. The UART interface supports configurable
data rates with the default at 9600 baud. Signal levels are related to the
VCC_IO
supply voltage. An interface
based on RS232 standard levels (+/- 7 V) can be realized using level shifter ICs such as the Maxim MAX3232.
Hardware handshake signals and synchronous operation are not supported.
A signal change on the UART RX pin can also be used to wake up the receiver in Power Save Mode (see the
u-blox 7 Receiver Description including Protocol Specification
[2].).
2.2.2
Display Data Channel (DDC) Interface
An I
2
C compatible Display Data Channel (DDC) interface is available for serial communication with a host CPU.
The SCL and SDA pins have internal pull-up resistors sufficient for most applications. However, depending on the
speed of the host and the load on the DDC lines additional external pull-up resistors might be necessary. For
speed and clock frequency see the
EVA-7M Data Sheet
To make use of DDC interface the
D_SEL
pin has to be left open.
The EVA-7M DDC interface provides serial communication with u-blox wireless modules. See the
specification of the applicable wireless module to confirm compatibility.
For more information about DDC implementation refer to the
u-blox 7 Receiver Description including Protocol
Specification
2.2.3
SPI Interface
The SPI interface can be used to provide a serial communication with a host CPU. If the SPI interface is used,
UART and DDC are deactivated, because they share the same pins.
