u-blox UBX-G7020 Hardware Integration Manual Download

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UBX-G7020 - Hardware Integration Manual

Summary of Contents for UBX-G7020

Page 1: ...ion Manual Highlights u blox 7 position engine featuring excellent accuracy and time to first fix performance Multi GNSS engine for GPS GLONASS Galileo and QZSS AssistNow Online Offline and Autonomous...

Page 2: ...kage Standard grade UBX G7020 KT A0100 A 1 00 N A UBX G7020 CT WL CSP50 Standard grade UBX G7020 CT A0100 A 1 00 N A UBX G7020 KA QFN40 package Automotive grade UBX G7020 KA A0100 A 1 00 N A This docu...

Page 3: ...production and final product tests Application Note This document provides general design instructions and information that applies to all u blox GPS receivers See section Related documents for a list...

Page 4: ...processed as soon as possible You will find the contact details at the end of the document Helpful information when contacting technical support When contacting Technical Support please have the foll...

Page 5: ...pins 18 2 2 3 Communication interfaces 19 2 2 4 Time pulse 21 2 2 5 External interrupt 21 2 2 6 SAFEBOOT_N Pin Safe Boot Mode 21 2 2 7 Active Antenna Supervisor 22 2 3 System reset 24 2 4 Clock gener...

Page 6: ...8 3 1 TCXO Y1 48 3 2 Crystal Y2 50 3 3 RTC crystal Y3 51 3 4 SQI flash U3 51 3 5 RF band pass filter F1 51 3 6 External LNA protection filter F2 52 3 7 USB line protection D1 52 3 8 USB LDO U3 52 3 9...

Page 7: ...ptional SQI flash 62 5 4 2 Test the GPS GNSS performance 63 5 4 3 System monitoring 63 Appendix 64 A Reference schematics 64 A 1 Cost optimized circuit 64 A 2 Best performance circuit 65 A 3 Power opt...

Page 8: ...few as 8 external components and the small footprint further reduces costs by enabling 2 layer PCB integration LDOs and an LNA are built in and costly external memory is not needed This makes UBX G702...

Page 9: ...ply Interfaces Ensure correct wiring rate and messages setup on the chipset and the host system Antenna interface For optimal performance seek short routing matched impedance and no stubs RF front end...

Page 10: ...voltage for the backup domain is generated by LDO_B and is either supplied by VDD_IO or in case of a power failure at VDD_IO by V_BCKP There is a voltage monitor at VDD_IO VDD_IO_OK which switches th...

Page 11: ...main needs the core domain to be alive 2 1 1 4 Clock domain The voltage for the clock domain is generated by LDO_X and is normally supplied by VDD_IO If the single crystal feature is enabled to provid...

Page 12: ...any series resistance 0 2 Ohm into V_CORE supply as it will generate input voltage noise owing to the dynamic current conditions 2 1 2 1 1 DC DC converter To improve the power consumption the supply...

Page 13: ...nt of a power failure at VDD_IO the backup domain will be supplied by V_BCKP Furthermore if the single crystal feature is enabled which derives the RTC frequency from the main clock it also supplies t...

Page 14: ...parts in the UBX G7020 VDD_LNA is the supply for the low noise amplifier inside the UBX G7020 VDD_ANA and VDD_LNA must be supplied by VDD_RF_OUT If a clean power supply cannot be provided at V_CORE w...

Page 15: ..._BCKP can be used to maintain RTC and backup RAM information even if VDD_IO fails 2 1 4 Operating Modes 2 1 4 1 Continuous Mode Continuous Mode uses the acquisition engine at full performance resultin...

Page 16: ...on pin In case PIO5 is GND no SQI flash used it acts as an oscillator configuration pin 4 SQI_CLK or CFG_OSC1 O I Clock for external SQI FLASH or configuration pin In case PIO5 is GND no SQI flash use...

Page 17: ...ogging see section 3 4 To run the firmware out of the SQI flash a minimum size of 4Mb is required A 4Mb device is also sufficient to save AssistNow Offline information plus the Low Level Configuration...

Page 18: ...ed All the configuration pins have internal pull ups Any left open equates to a logical 1 PIO5 Configuration Remarks 1 open Configuration pins disabled The configuration done by PIO0 to PIO4 is ignore...

Page 19: ...Communication Interfaces overview It is not possible to have both the DDC and SPI interfaces active simultaneously for communication with a host For debugging purposes it is recommended to have a seco...

Page 20: ...erface PIO10 D_SEL has to be connected to GND 2 2 3 4 Electromagnetic interference on interface signal lines Any interface signal line length 3 mm may pick up high frequency signals and transfer this...

Page 21: ...w at start up the UBX G7020 will start up in Safe Boot Mode and will not enter GPS GNSS operation In Safe Boot Mode the UBX G7020 runs from an internal ring oscillator and starts regardless of any con...

Page 22: ...ow Antenna not OK Polarity can be changed by Low Level Configuration if the external circuitry requires other polarity see section 2 10 2 PIO16 ANT_OFF O Control signal to turn on and off the antenna...

Page 23: ...and off the antenna supply high turn off antenna supply low short to GND Polarity can be changed by Low Level Configuration if the external circuitry requires other polarity see section 2 10 2 Table...

Page 24: ...e system without affecting the temporary GNSS GPS data saved in the backup memory Thus AssistNow Autonomous data time information and ephemeris will still be available Leave RESET_N open for normal op...

Page 25: ...tal or TCXO reference frequency behavior is essential for the overall GPS GNSS system performance To enable fast weak signal acquisition tolerances on the crystal specifications have to be tightened T...

Page 26: ...onance apart from the desired thickness shear mode Coupled modes often referred to as activity dips occur when two or more excited modes or normally their harmonics beat together Face shear flexure th...

Page 27: ...ally it can be said that a crystal designed for high load capacitance will have a lower Pullability value than one designed for a lower load capacitance However high load capacitance values require hi...

Page 28: ...rejected significantly if using LDO_X_OUT to supply a TCXO The correct LDO_X_OUT voltage has to be set by Low Level Configuration The LDO_X_OUT voltage has to be set by the Low Level Configuration to...

Page 29: ...sed in conjunction with a 1 8V TCXO the TCXO must not be supplied by LDO_X_OUT Instead the TCXO has to be supplied directly from VDD_IO LDO_X_OUT is used to enable and disable the TCXO respectively Fi...

Page 30: ...ncy 26MHz This feature is called single crystal operation In addition the TCXO or XTO see section 2 4 will be supplied by the backup battery at V_BCKP in the event of a power failure at VDD_IO Consequ...

Page 31: ...or TimeMark see the u blox 7 Receiver Description including Protocol Specification 3 For Power Save Mode operations where the RTC is needed the time aiding cannot be used Because the host does not ha...

Page 32: ...nents centered at 1602MHz and a bandwidth of about 10MHz So it might be a challenge especially for the antenna to get good performance on GPS and GLONASS signals with the same receiver 2 6 1 General n...

Page 33: ...GSM usually does not affect GPS GNSS performance but may be destructive due to the high peak power levels 2 6 1 1 In band interference mitigation With in band interference the signal frequency is ver...

Page 34: ...ectrical signals and hence the RF input needs to be protected accordingly The following points should be considered seriously in order to determine the appropriate RF input circuitry 1 Is the design u...

Page 35: ...n board layout the values may need to be adjusted to provide a 50 Ohm input impedance Starting values are provided in sections 3 14 and 3 16 C1 is a DC block Figure 17 LNA input matching ESD discharge...

Page 36: ...orrect operation of the ANT_OFF_N signal at PIO16 2 6 2 3 Improved jamming immunity If the UBX G7020 is exposed to an interference environment it is recommended to use additional filtering Improved in...

Page 37: ...red to ensure correct operation of the ANT_OFF_N signal at PIO16 2 6 2 4 RF front end using an active antenna Active antennas for GPS GNSS application are usually powered through a DC bias on the RF c...

Page 38: ...settings and held permanently in external SQI flash or internal eFuse see section 2 10 2 In order to get the 90 ohm differential impedance in between the USB_DM and USB_DP data line a 27ohm series re...

Page 39: ...ce can be used for testing and debugging This interface allows failure analysis by the factory and boundary scan in production test Pin Function Remarks TDI PIO13 Test Data Input Shared with PIO13 TDO...

Page 40: ...other digital circuits on the board A proper GND concept shall be followed The RF section should not be subject to noisy digital supply currents running through its GND plane Care must also be exercis...

Page 41: ...d into via holes during reflow The landing pads for the exterior pads extend slightly beyond the maximum package dimensions The checkerboard pattern of the solder mask opening ensures even distributio...

Page 42: ...ive Specification Page 42 of 74 2 9 2 2 WL CSP50 Package Figure 24 QFN40 UBX G7020 CT recommended copper land pattern Figure 25 QFN40 UBX G7020 CT recommended solder mask opening pattern For mechanica...

Page 43: ...n not start up at all All the Low Level Configurations can be set in the eFuse inside the UBX G7020 chip If an SQI Flash is connected to the UBX G7020 a partial Low Level Configuration i e all except...

Page 44: ...ash or eFuse see u blox 7 Receiver description including protocol specification 3 The VDD_IO threshold POR_IO which has to match the supply voltage of the SQI flash must be always configured in eFuse...

Page 45: ...l Configuration set by the eFuse If the SQI flash is only used to log data the Low Level Configuration cannot be saved in the SQI flash Only if the firmware runs from the SQI flash can the Low Level C...

Page 46: ...S G7 HW 10003 Objective Specification Page 46 of 74 2 10 2 4 Low Level Configuration applying sequence Figure 26 Low level configuration applying sequence The Low Level Configuration can be checked wi...

Page 47: ...or the SQI flash if present If the Functional Configuration is saved to backup memory without its associated backup battery i e V_BCKP not supplied independently from VDD_IO then if VDD_IO fails the...

Page 48: ...ift over 1 year 1 0 ppm 1 13 Long term stability frequency drift over 2 years 2 0 ppm 1 14 Long term stability frequency drift over 10 years 4 0 ppm 1 15 G Sensitivity all 3 axes random vibration 30 H...

Page 49: ...C 85 C 6 Manufacturing information 6 1 Solder Process Able to withstand solder reflow process min 3 Cycles 240 C 20 s 6 2 Packaging description Tape and Reel Table 13 TCXO specifications Manufacturer...

Page 50: ...ency DLD 12 0 6 2 7 Equivalent series resistance ESR 15 60 3 Electrical Specifications 3 1 Shock Half sine wave acceleration of 100 G peak amplitude for 11 ms duration 3 cycles each plane 3 2 Vibratio...

Page 51: ...016 3V 16Mb several package temperature options SST SST26VF032 3V 32Mb several package temperature options Spansion S25FL004K 3V 4Mb several package temperature options Spansion S25FL008K 3V 8Mb sever...

Page 52: ...B9850 GPS Compliant to the AEC Q200 standard CTS CER0032A GPS Ceramic filter also offers robust ESD Protection Table 21 Recommended parts for the LNA protection filter 3 7 USB line protection D1 Manu...

Page 53: ...enna supervisor switch transistor T1 Manufacturer Order No Vishay Si1016X T1 E3 Table 29 Recommend parts list for antenna supervisor switch transistor p channel MOSFET 3 14RF inductors Name Use Figure...

Page 54: ...ling VDD_LNA VDD_ANA Figure 5 X5R 1U0 10 6 3V C4 Decoupling LDO_RF_OUT Figure 2 X5R 1U0 10 6 3V C5 Decoupling LDO_X_OUT Figure 2 X5R 1U0 10 6 3V C6 Decoupling V_CORE DCDC converter used Figure 3 X5R 4...

Page 55: ...0 1W R6 Antenna supervisor voltage divider Figure 8 100K 5 0 1W R7 Pull down at LNA enable Figure 18 10K 5 0 1W Table 35 Standard resistors 3 18Ferrite beads FB1 Manufacturer Order No Comments MuRata...

Page 56: ...eck The Layout Design In Checklist also helps to avoid an unnecessary re spin of the PCB and helps to achieve the best possible performance Basically the checklist lists the recommendation from the pr...

Page 57: ...open if not used 19 A5 PIO6 O UART TX SPI MISO UART TX or SPI MISO leave open if not used 20 C6 T_SENSE I O Temperature sensing Leave open 21 A7 V_DCDC_IN I DCDC converter input Connect to V_DCDC_O a...

Page 58: ...OUT voltage Section 2 2 2 SQI flash size and type are chosen correctly regarding application means use of SQI flash firmware and or logging Section 3 4 RF section Interference ESD and RF power maximum...

Page 59: ...GPS G7 HW 10003 Objective Specification Page 59 of 74 GPS GNSS Crystal oscillator section is shielded by a GND guard ring Section 2 9 1 RF signal lines are kept as short as possible and are designed a...

Page 60: ...andling Particular care must be used when handling patch antennas due to the risk of electrostatic charges In addition to standard ESD safety practices the following measures should be taken into acco...

Page 61: ...details on how to set the configuration see section 2 10 Programming the SQI flash can be accomplished using either u center the u blox GPS GNSS evaluation software or via a firmware update utility A...

Page 62: ...S G7 HW 10003 Objective Specification Page 62 of 74 5 4 1 Set the Low Level Configuration and program the optional SQI flash Figure 28 Sequence in production to set the Low Level Configuration and pro...

Page 63: ...ed if crystal is used Doppler 4000 Hz 19000 Hz 4000 Hz 19000 Hz It is mandatory that the frequency of the TCXO crystal is within these limits Make sure that the used single channel simulator has no do...

Page 64: ...cation Page 64 of 74 Appendix A Reference schematics A 1 Cost optimized circuit Firmware runs out of ROM Passive antenna Crystal Single crystal feature used RTC derived from main clock UART and DDC fo...

Page 65: ...ication Page 65 of 74 A 2 Best performance circuit 1 8V TCXO supplied by LDO_X_OUT External LNA RTC crystal Filtering for LNA supply UART and DDC interface Figure 30 Best performance circuit VDD_IO su...

Page 66: ...ration Manual Appendix GPS G7 HW 10003 Objective Specification Page 66 of 74 A 3 Power optimized circuit DCDC converter Crystal RTC crystal SPI interface No SQI flash Figure 31 Power optimized circuit...

Page 67: ...74 A 4 Improved jamming immunity External SAW filter LNA SAW filter DCDC converter 1 8V TCXO supplied by LDO_X_OUT RTC crystal UART and DDC interface Figure 32 Standard circuit for an improved jamming...

Page 68: ...ndix GPS G7 HW 10003 Objective Specification Page 68 of 74 A 5 1 8V design using TCXO 1 8V TCXO UART and DDC interface RTC crystal UART and DDC interface External LNA Figure 33 Standard circuit using...

Page 69: ...0003 Objective Specification Page 69 of 74 A 6 Circuit using active antenna Active antenna 3V TCXO UART and DDC RTC crystal Figure 34 Standard circuit using active antenna VDD_IO supply must be higher...

Page 70: ...GPS G7 HW 10003 Objective Specification Page 70 of 74 A 7 USB self powered circuit 1 8V TCXO USB External LNA RTC SQI flash Figure 35 USB self powered circuit VDD_IO supply must be higher than 2 1V be...

Page 71: ...tegration Manual Appendix GPS G7 HW 10003 Objective Specification Page 71 of 74 A 8 USB bus powered circuit 1 8V TCXO USB DCDC converter External LNA RTC SQI flash Figure 36 USB bus powered circuit C...

Page 72: ...dix GPS G7 HW 10003 Objective Specification Page 72 of 74 A 9 Circuit using 3 pin antenna supervisor 3 pin antenna supervisor RTC Crystal UART and DDC interface SQI flash Figure 37 Circuit using 3 pin...

Page 73: ...blox 7 Receiver description including protocol specification Docu No GPS G7 SW 12002 4 http www murata com products emc knowhow index html 5 http www murata com products emc knowhow pdf 4to5e pdf For...

Page 74: ...5 E mail support_us u blox com Europe Middle East Africa u blox AG Phone 41 44 722 74 44 E mail info u blox com Technical Support Phone 41 44 722 74 44 E mail info u blox com Asia Australia Pacific u...

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