NORA-W2 series - Hardware integration manual
UBX-22005177 - R01
Design-in
Page 21 of 61
C1
–
Public
3.3
General layout guidelines
These guidelines describe best schematic and layout practices for integrating the module on a host
application board, as described in
Designers should prioritize the layout of higher speed buses. Low frequency signals, other than
those with high-impedance traces, are generally not layout critical.
⚠
Low frequency signals with high-impedance traces (such as signals driven by weak pull resistors)
may be affected by crosstalk. For these high impedance traces, a supplementary isolation of 4*W
from other busses is recommended.
3.3.1
Considerations for schematic design and PCB floor-planning
•
Verify which signal bus requires termination and add series resistor terminations to the
schematics.
•
Carefully consider the placement of the module with respect to antenna position and host
processor.
•
Verify with PCB manufacturer allowable stack-ups and controlled impedance dimensioning.
•
Verify that the power supply design and power sequence are compliant with the specification of
NORA-W2 series module.
3.3.2
Component placement
•
Accessory parts like bypass capacitors should be placed as close as possible to the module to
improve filtering capability, prioritizing the placement of the smallest size capacitor close to
module pads.
•
Do not place components close to the antenna area. Follow the recommendations of the antenna
manufacturer to determine distance of the antenna in relation to other parts of the system.
Designers should also maximize the distance of the antenna to High-frequency busses, like DDRs
and related components. Alternatively, consider an optional metal shield to reduce interferences
that might otherwise be picked up by the antenna and subsequently reduce module sensitivity.
•
An optimized module placement allows better RF performance. For more information about the
module placement and other antenna considerations, see also
Antenna interface
.
3.3.3
Layout and manufacturing
•
Avoid stubs on high-speed signals. Test points or component pads should be placed over the PCB
trace.
•
Verify the recommended maximum signal skew for differential pairs and length matching of buses.
•
Minimize the routing length; longer traces degrade signal performance. Ensure that maximum
allowable length for high-speed busses is not exceeded.
•
Ensure to track your impedance matched traces. Consult early with your PCB manufacturer for
proper stack-up definition.
•
RF, analog, and digital sections should have dedicated and clearly separated areas on the board.
•
No digital routing is allowed in the GND reference plane area of RF traces (ANT pins and Antenna).
•
Designers are strongly recommended to avoid digital routing beneath all layers of RF traces.
•
Ground cuts or separation are not allowed below the module.
•
As a first priority, minimize the length of the RF traces. Then, minimize bus length to reduce
potential EMI issues related to the radiation of digital busses.
•
All traces (Including low speed or DC traces) must couple with a reference plane (GND or power).
High-speed busses should be referenced to the ground plane. If designers need to change the
ground reference, some capacitors should be added and an adequate number of GND vias must
be added in the area of transition. This facilitates a low-impedance path between the two GND
layers for the return current.
