LEXI-R422 - System integration manual
UBX-23007449 - R02
Design-in
Page 75 of 108
C1-Public
Additional considerations
If a 3.0 V Application Processor (DTE) is used, the voltage scaling from any 3.0 V output of the DTE to
the corresponding 1.8 V input of the module (DCE) can be implemented as an alternative low-cost
solution, by means of an appropriate voltage divider. Consider the value of the pull-down / pull-up
integrated at the input of the module (DCE) for the correct selection of the voltage divider resistance
values. Make sure that any DTE signal connected to the module is tri-stated or set low when the
module is in power-down mode and during the module power-on sequence (at least until the activation
of the
V_INT
supply output of the module), to avoid latch-up of circuits and allow a clean boot of the
module (see the remark below).
Moreover, the voltage scaling from any 1.8 V output of the cellular module (DCE) to the corresponding
3.0 V input of the Application Processor (DTE) can be implemented by means of an appropriate low-
cost non-inverting buffer with open drain output. The non-inverting buffer should be supplied by the
V_INT
supply output of the cellular module. Consider the value of the pull-up integrated at each input
of the DTE (if any) and the baud rate required by the application for the appropriate selection of the
resistance value for the external pull-up biased by the application processor supply rail.
☞
The
TXD
data input line of the module has an internal active pull-up enabled.
☞
Do not apply voltage to any UART interface pin before the switch-on of the UART supply source,
which is the
V_INT
supply of the module.
☞
ESD sensitivity rating of the UART interface pins is 1 kV (HBM according to JS-001-2017). Higher
protection levels could be required if the lines are externally accessible and it can be achieved by
mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) close to the accessible
points.
2.6.1.2
Guidelines for UART layout design
The UART serial interface requires the same consideration regarding electro-magnetic interference
as any other digital interface. Keep the traces short and avoid coupling with RF line or sensitive analog
inputs, since the signals can cause the radiation of some harmonics of the digital data frequency.
2.6.2
USB interface
2.6.2.1
Guidelines for USB circuit design
The
USB_D+
and
USB_D-
lines carry the USB serial data and signaling. The lines are used in
single-ended mode for full speed signaling handshake, as well as in differential mode for high speed
signaling and data transfer.
USB pull-up or pull-down resistors and external series resistors on
USB_D+
and
USB_D-
lines as
required by the USB 2.0 specification
are part of the module USB pins driver and do not need to be
externally provided.
Routing the USB pins to a connector, they will be externally accessible on the application device.
According to EMC/ESD requirements of the application, an additional ESD protection device with very
low capacitance should be provided close to accessible point on the line connected to this pin, as
described in
☞
USB interface pins ESD sensitivity rating is 1 kV (HBM according to JS-001-2017). Higher
protection level could be required if the lines are externally accessible and it can be achieved by
mounting an ultra-low capacitance (i.e. < 1 pF) ESD protection (e.g. Littelfuse PESD0402-140 ESD
protection device) on the lines connected to these pins, close to accessible points.
