LARA-R2 series - System Integration Manual
UBX-16010573 - R12
Design-in
Page 112 of 157
2.6.4
DDC (I
2
C) interface
2.6.4.1
Guidelines for DDC (I
2
C) circuit design
General considerations
Communication with u-blox GNSS receivers over DDC (I
2
C) is not supported by the LARA-R204-02B and
LARA-R211-02B-00 product versions.
The “GNSS RTC sharing” function is not supported by the “02” and “62” product versions.
The DDC I
2
C-bus master interface can be used to communicate with u-blox GNSS receivers and other external
I
2
C-bus slaves as an audio codec. Beside the general considerations explained below, see:
the following parts of this section for specific guidelines for the connection to u-blox GNSS receivers.
section 2.7.1 for an application circuit example with an external audio codec I
2
C-bus slave.
To be compliant to the I
2
C-bus specifications, the module bus interface pins are open drain output and pull-up
resistors must be mounted externally. Resistor values must conform to
I
2
C bus specifications
[11]: for example, 4.7
k
resistors can be commonly used. Pull-ups must be connected to a supply voltage of 1.8 V (typical), since this is
the voltage domain of the DDC pins which are not tolerant to higher voltage values (e.g. 3.0 V).
Connect the DDC (I
2
C) pull-ups to the
V_INT
1.8 V supply source, or another 1.8 V supply source enabled
after
V_INT
(e.g. as the GNSS 1.8 V supply present in Figure 62 application circuit), as any external signal
connected to the DDC (I
2
C) interface must not be set high before the switch-on of the
V_INT
supply of the
DDC (I
2
C) pins, to avoid latch-up of circuits and permit a proper boot of the module.
The signal shape is defined by the values of the pull-up resistors and the bus capacitance. Long wires on the bus
increase the capacitance. If the bus capacitance is increased, use pull-up resistors with a nominal resistance value
lower than 4.7 k
, to match the
I
2
C bus specifications
[11] regarding the rise and fall times of the signals.
Capacitance and series resistance must be limited on the bus to match the I
2
C specifications (1.0 µs is the
maximum allowed rise time on the
SCL
and
SDA
lines): route connections as short as possible.
The ESD sensitivity rating of the DDC (I
2
C) pins is 1 kV (Human Body Model according to JESD22-A114).
A higher protection level could be required if the lines are externally accessible and it can be achieved by
mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) close to accessible points.
If the pins are not used as DDC bus interface, they can be left unconnected.
