TE0808 TRM
Revision: v.32
Copyright © 2019 Trenz Electronic GmbH
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8.3 Power-On Sequence Diagram
The TE0808 SoM meets the recommended criteria to power up the Xilinx Zynq Ult MPSoC properly by
keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular Power Domains
and powering up the on-board voltages.
The on-board voltages of the TE0808 SoM will be powered-up in order of a determined sequence by activating the
above-mentioned power rails and the Enable-Signals of the DC-DC converters. The on-board voltages will be
powered up at three steps.
1. Low-Power Domain (LPD) and on-board Si5345A programmable clock generator supply voltage
2. Programmable Logic (PL) and Full-Power Domain (FPD)
3. GTH, PS GTR transceiver and DDR memory
Hence, those three power instances will be powered up consecutively and the Power-Good-Signals of the previous
instance has to be asserted.
Following diagram describes the sequence of enabling the three power instances utilizing the DC-DC converter
control signals (Enable, Power-Good), which will power-up in descending order as listed in the blocks of the
diagram.
