Trenz Electronic TE0808 TRM, Manual

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TE0808 TRM Revision: v.32
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2
https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf
3
https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf
Table 4 : B2B connector pin-out of JTAG interface.
5.4 Configuration Bank Control Signals
The Xilinx Zynq Ult MPSoC's PS configuration bank 503 control signal pins are accessible through B2B
connector J2.
For further information about the particular control signals and how to use and evaluate them, refer to the Xilinx
Zynq Ult MPSoC TRM
2
and UltraScale Architecture Configuration - User Guide
3
.
Signal B2B Connector Pin Function
DONE J2-116 PL configuration completed.
PROG_B J2-100 PL configuration reset signal.
INIT_B J2-98 PS is initialized after a power-on reset.
SRST_B J2-96 System reset.
MODE0 ... MODE3 J2-109/J2-107/J2-105/
J2-103 4-bit boot mode pins.
For further information about the boot
modes refer to the Xilinx Zynq
Ult MPSoC TRM section 'Boot
and Configuration'.
ERR_STATUS /
ERR_OUT J2-86 / J2-88 ERR_OUT signal is asserted for
accidental loss of power, an error, or
an exception in the MPSoC's Platform
Management Unit (PMU).
ERR_STATUS indicates a secure lock-
down state.
PUDC_B J2-127 Pull-up during configuration (pulled-up
to PL_1V8).
Table 5 : B2B connector pin-out of MPSoC's PS configuration bank.
5.5 Analog Input
The Xilinx Zynq Ult MPSoC provides differential pairs for analog input values. The pins are exposed to B2B-
connector J2.