TE0600 TRM
Revision: V3.02
Copyright © 2017 Trenz Electronic GmbH
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Module revisions and assembly variants
Module revision coded by 4 FPGA BR[3:0] pins, which can be read by FPGA firmware. All these pins should
be configured to have internal PULLUP.
Signal
FPGA pin
BR3
R19
BR2
P18
BR1
N16
BR0
P17
Revision 01
1
1
1
1
Revision 02
1
1
1
0
Revision 03
1
1
0
1
Board revisions pin coding
Main differences between 01 and 02 revisions:
More powerful regulators for 1.2V and 1.5V rails
VCCAUX separated from 2.5V power rail
128Mbit SPI Flash
Additional secure 1Kbit EEPROM
Optional B2B connection to bank 2 differential clock input
Main differences between 02 and 03 revisions:
Optimized placement and routing for DC/DC converters
Added thermal vias to mounting holes
Added Testpoints
Changed Board revision identification to REV03
Changed U9 from SIT1602AI-83-33E-25.0000 to SiT8008AI-73-XXS-25.000000E
Added Track-it™ Traceability Pad
Change SPI Flash from W25Q128BVEIG to W25Q128FVEIG
DDR3 changed from IM4G16D3EABG-125I to IM4G16D3FABG-125I for the 4 GBit variants
U13 () is no longer populated by default
Module assembly variants coded by 4 zero ohm resistors, connected to FPGA AV[3:0] pins. All these pins
should be configured to have internal PULLUP.
Signal
FPGA pin
AV3
M18
AV2
M17
AV1
V20
AV0
U19
Speed
grade
SDRAM
Temp
grade
Status
TE0600-02[V|B]
0
0
0
0
2
2x128MBit
C
obsolete
TE0600-02[V|B]I
0
0
0
1
2
2x128MBit
I
obsolete
TE0600-02[V|B]F
0
0
1
0
3
2x128MBit
C
obsolete
TE0600-02[V|B]IF
0
0
1
1
3
2x128MBit
I
obsolete
TE0600-02[V|B]MF
0
1
0
0
3
2x512MBit
C
obsolete
