Transmeta Crusoe TM5500, System Design Manual

Page: 52 / 130

July 17, 2002
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DDR Memory Design
The frequency setting for the DDR SDRAM interface is initialized during the boot sequence from data stored
in the configuration ROM. DDR interface frequency settings vary at each LongRun power management step.
DDR interface timing specifications and operating frequencies at various LongRun power management steps
are provided in the
Data Book . The Data Book also provides DDR memory interface configuration constraints,
as well as recommended and example system memory configurations. See the OEM Configuration Table
chapter of the Development and Manufacturing Guide for further LongRun configuration and memory
frequency information.
4.2 Clock Enable Isolation
The processor DDR_CKE clock enable signals must be isolated from the DDR SDRAM. This is because
power states exist where the processor is powered down and the DDR SDRAM remains powered (e.g. STR).
Since TM5500/TM5800 processors do not have a suspend power well, output signals are undefined during
power transitions and subject to glitching. The SUSPEND_STATUS signal from the southbridge remains
asserted while in STR mode, and is therefore used to control the isolation switches.
4.3 Signal Termination
Series termination is recommended on all signals. Termination impedance should be calculated on a per-
design basis.