Transmeta Crusoe TM5500, System Design Manual

Page: 42 / 130

July 17, 2002
42
Processor Power Supplies and Power
Management
3.5 State Transition Timing Requirements
This section describes the state transition timing requirements for TM5500/TM5800 processors. Note that the
various signal names used in this document are typically written from the perspective of the processor. For
example, STPCLK# and SLEEP# refer to the processor input signals for Stop Clock and Sleep.
ACPI Active State (C0)
The details of the TM5500/TM5800 processor power-on sequence are described in the Data Book and
associated references. Only the timing diagram and critical latencies for the power-on sequence are provided
here.
Parameter Description Min Max Diagram Note
t
vdd_rise
Supply delay and rise time
1
1. Refer to Figure 4 and Table 10 for details on power supply sequencing timing.
- 250 mS T1
t
vdd_pg
POWERGOOD asserted after supplies
reach 95% of final value 0 S - T2
t
vdd_prst
Supplies stable prior to PCI_RST#
deasserted 1 mS - T3
t
pclk_prst
PCI_CLK stable prior to PCI_RST#
deasserted 100 µS - T4
t
clk_prst
CLKIN stable prior to PCI_RST#
deasserted 1 mS - T5
t
prst_rst
PCI_RST# deasserted to RESET#
deasserted 0 S - T6
t
pg_rst
POWERGOOD asserted to RESET#,
PCI_RST# deasserted 1 mS - T7
t
pg_low
POWERGOOD inactive pulse width 10 CLKINs - not shown
- Clocks off to POWERGOOD deassertion 0 nS - T9
- POWERGOOD deassertion to
PCI_RST# and RESET# assertion 0 nS - T10
- POWERGOOD to all voltages off 0 nS - T11