Preliminary User's Manual l TQMaX4XxL UM 0001 l © 2022, TQ-Systems GmbH
Page 14
3.2.6
Secure Element
A Secure Element Chip can optionally be fitted on the TQMaX4XxL. The connection can be seen in the following figure:
Figure 10:
Block diagram SEC
The SE050C2HQ1/Z01 from NXP is used as the secure element. All I²C addresses are described in chapter 3.2.8.7.
3.2.7
Temperature sensor
A temperature sensor is placed on the TQMaX4XxL to monitor the module temperature.
The over temperature output (TEMP_ALERT) of the sensor is available at the LGA balls as an open drain output.
The I²C addresses are described in chapter 3.2.8.7.
3.2.8
Interfaces
In general, except for the memory connection, all IO pins of the CPU are provided at the LGA pads.
For further information about the interfaces and the pin multiplexing refer to the CPU Reference Manual (3).
3.2.8.1
Ethernet switch
The AM64x / AM243x provides an integrated Ethernet switch (CPSW3G) supporting:
•
Up to 2 Ethernet ports
o
RMII (10/100)
o
RGMII (10/100/1000)
•
IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
•
Clause 45 MDIO PHY management
•
Energy efficient Ethernet (802.3az)
CPSW3G MDIO0, CPSW3G RMII1, CPSW3G RMII2, and CPSW3G RGMII1 have one or more signals which can be multiplexed to
more than one pin. Timing requirements and switching characteristics are only valid for specific pin combinations known as
IOSETs. Valid pin combinations or IOSETs for these interfaces are shown in the AM64x / AM243x data sheets (1) (2).
3.2.8.2
PRU_ICSSG
The Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU_ICSSG) of the AM64x / AM243x
provides flexible industrial communications capability including full protocol stacks for EtherCAT slave, PROFINET device,
EtherNet/IP adapter, and IO-Link Master. The PRU-ICSSG further provides capability for gigabit and TSN based protocols. In
