Preliminary Preliminary User's Manual l TQMaX4XxL UM 0001 l © 2022, TQ-Systems GmbH
Page 11
Note: Update
When designing a mainboard, it is recommended to plan a redundant update concept for software
updates in the field. Furthermore, it is recommended to switch the conversion of the boot strap pins to
high impedance after reading in.
3.2.3
Memory
3.2.3.1
LPDDR4 SDRAM
The TQMaX4XxL has an LPDDR4 memory with the use of in-line ECC:
•
16-bit bus width with optional ECC (8-bit data + 8-bit ECC)
•
Up to 1600 Mbps = 800 MHz
•
1 GByte / 2 GByte
Figure 5: Block diagram DDR3L SDRAM connection
3.2.3.2
eMMC
An eMMC is available to the TQMaX4XxL as non-volatile data memory for programs and data (e.g. boot loader, operating
system). The used MMC0 signals are not available to the Pinout.
•
MMC0 Interface is connected to the eMMC Flash
•
RESETSTATz is used to reset the eMMC
•
8 / 16 / 32 / 64 GByte
Figure 6: Block diagram eMMC flash interface
The TQMaX4XxL supports the following transmission modes:
Table 7: eMMC Flash modes
Mode
1-bit
4-bit
8-bit
Note
Default Speed
TBD
TBD
TBD
High Speed
TBD
TBD
TBD
Boot process
HS200
TBD
TBD
TBD
U-boot
HS400
TBD
TBD
TBD
Linux
