TQ TQMaX4X Series, Prelimenary Manual

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Preliminary User's Manual l TQMaX4XxL UM 0001 l © 2022, TQ-Systems GmbH Page 24
3.3.2 Pinout TQMaX4XxL (continued)
Table 32: TQMaX4XxL pad description (continued)
P21 RTC_INT# - O
I2C Devices
RTC Interrupt, Open-Drain. Pullup
required (typ. 10kΩ)
1.8 V /
3.3V
P22 RTC_CLK_OUT - O RTC Clock Output 1.8 V
M19 TEMP_ALERT - O
Programmable Alert Output, Open-
Drain. Pullup required (typ. 5kΩ)
1.8 V /
3.3 V
L19 CUST_EEPROM_WC# - I
Customer EEPROM Write
Protection Control
1.8 V
B22 SE_ISO7816_IO1 - IO
SEC Interface 1.8 V
C21 SE_ISO7816_IO2 - IO
B20 SE_ISO7816_CLK - I
A21 SE_ISO7816_RST# - I
D21 SE_ISO14443_LA - IO
C22 SE_ISO14443_LB - IO
A20 SE_ENA - I
Main domain
AB11
GPMC0_CLK R17 O
IO
Multiplexing
Options
Signal balls with a Pad
Configuration Register can be
configure as GPIO input and
internal pulldown other-wise left
unconnected
1.8 V
Y10 GPMC0_AD0 T20 IO
AA10 GPMC0_AD1 U21 IO
W9 GPMC0_AD2 T18 IO
AA9 GPMC0_AD3 U20 IO
AB9 GPMC0_AD4 U18 IO
W8 GPMC0_AD5 U19 IO
Y8 GPMC0_AD6 V20 IO
AB8 GPMC0_AD7 V21 IO
Y7 GPMC0_AD8 V19 IO
AA7 GPMC0_AD9 T17 IO
W6 GPMC0_AD10 R16 IO
AA6 GPMC0_AD11 W20 IO
AB6 GPMC0_AD12 W21 IO
W5 GPMC0_AD13 V18 IO
Y5 GPMC0_AD14 Y21 IO
AB5 GPMC0_AD15 Y20 IO
AB12 GPMC0_CS0# R19 O
AA12 GPMC0_CS1# R20 O
W12 GPMC0_CS2# P19 O
W11 GPMC0_CS3# R21 O
Y11 GPMC0_ADV#_ALE P16 O
V10 GPMC0_BE0#_CLE P17 O
V9 GPMC0_BE1# T19 O
U8 GPMC0_DIR N17 O
U5 GPMC0_WAIT0 W19 I
V4 GPMC0_WAIT1 Y18 I
U7 GPMC0_WP# N16 O
V7 GPMC0_OE#_RE# R18 O
V6 GPMC0_WE# T21 O
U22 SPI0_CLK D13 IO
T21 SPI0_D0 A13 O
T20 SPI0_D1 A14 I
U21 SPI0_CS0 D12 O
U19 SPI0_CS1 C13 O
V22 SPI1_CLK C14 IO
V20 SPI1_D0 B15 O
V19 SPI1_D1 A15 I
W21 SPI1_CS0 B14 O
W20 SPI1_CS1 D14 O
A17 UART0_RXD D15 I
B17 UART0_TXD C16 O
D17 UART0_CTS# B16 I
E17 UART0_RTS# A16 O