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Preliminary User's Manual  l  TQMaX4XxL UM 0001  l  © 2022, TQ-Systems GmbH 

 

Page  22 

 

 

3.3.2

 

Pinout TQMaX4XxL 

The following table shows the pad-out as top view through the TQMaX4XxL.  

 

Table 13: 

Pinout TQMaX4XxL, top view through TQMaX4XxL 

 

AA 

AB 

 

22 

 

SE_ISO 

7816 
_IO1 

SE_ISO 

14443 

_LB 

GND 

MCU_ 

SPI0 

_CLK 

MCU_ 

SPI0 

_D0 

GND 

MCU_ 

SPI1 

_CLK 

MCU_ 

SPI1 

_D0 

GND 

V_RTC 

_IN 

V_ 

VPP 

GND 

RTC_ 

CLK 

OUT 

RESET 

STATz 

GND 

SPI0 

_CLK 

SPI1 

_CLK 

GND 

ADC0_ 

AIN6 

ADC0 

_AIN5 

 

22 

21 

SE_ISO 

7816 

_RST# 

GND 

SE_ISO 

7816 
_IO2 

SE_ISO 

14443 

_LA 

GND 

MCU_ 

SPI0 

_D1 

MCU_ 

SPI1 

_CS0 

GND 

MCU_ 

SPI1 

_D1 

V_1V8 

GND 

GND 

V_3V3 

RTC_ 

INT# 

GND 

SPI0 

_D0 

SPI0 

_CS0 

GND 

SPI1 

_CS0 

ADC0 

_AIN7 

GND 

ADC0 

_AIN4 

21 

20 

SE_ 

ENA 

SE_ISO 

7816 

_CLK 

GND 

MCU_ 

SPI0 

_CS0 

MCU_ 

SPI0 

_CS1 

GND 

MCU_ 

SPI1 

_CS1 

MCU_ 

I2C0 

_SDA 

GND 

I2C1 

_SDA 

I2C1 

_SCL 

I2C0 

_SDA 

I2C0 

_SCL 

GND 

RESET 

_REQz 

SPI0 

_D1 

GND 

SPI1 

_D0 

SPI1 

_CS1 

GND 

ADC0 

_AIN3 

ADC0 

_AIN2 

20 

19 

GND 

MCU_ 

UART0 

_RXD 

MCU_ 

UART0 

_TXD 

GND 

MCU_ 

UART0 

_CTS# 

MCU_ 

UART0 

_RTS# 

GND 

MCU_ 

I2C1 

_SCL 

MCU_ 

I2C0 

_SCL 

GND 

CUST_ 

EEPROM 

_WC# 

TEMP_ 

ALERT 

GND 

MCU_ 

RESETz 

MCU_ 

RESET 

STATz 

GND 

SPI0 

_CS1 

SPI1 

_D1 

GND 

V_VDD 

SHV5 

ADC0 

_AIN1 

GND 

19 

18 

MCU_ 

UART1 

_RXD 

GND 

MCU_ 

UART1 

_TXD 

MCU_ 

UART1 

_CTS# 

GND 

MCU_ 

UART1 

_RTS# 

MCU_ 

I2C1 

_SDA 

GND 

EMU1 

EMU0 

TRST# 

TDI 

TCK 

TDO 

GND 

TMS 

V_RTC 

GND 

EXT_ 

REF 

CLK1 

MCU_ 

SAFETY_ 

ERROR# 

GND 

ADC0 

_AIN0 

18 

17 

UART0 

_RXD 

UART0 

_TXD 

GND 

UART0 

_CTS# 

UART0 

_RTS# 

- TQMaX4XxL - 

Top view - through PCB

 

ECAP0 

_IN_AP 

WM_OUT 

EXT 

INT# 

GND 

MCAN0 

_RX 

MCAN0 

_TX 

17 

16 

GND 

UART1 

_RXD 

UART1 

_TXD 

GND 

UART1 

_RTS# 

OSPI0 

_LB 

CLKO 

GND 

MCAN1 

_RX 

MCAN1 

_TX 

GND 

16 

15 

PRG0_ 

MDIO0 

_MDC 

GND 

PRG0_ 

MDIO0_ 

MDIO 

UART1 

_CTS# 

GND 

GND 

MMC1_ 

SDCD 

MMC1_ 

CMD 

GND 

MMC1 

_CLK 

15 

14 

PRG0_ 
PRU0_ 

GPO0 

PRG0_ 
PRU0_ 

GPO1 

GND 

PRG0_ 
PRU0_ 

GPO2 

PRG0_ 
PRU0_ 

GPO3 

OSPI0 

_CS1# 

MMC1_ 

SDWP 

GND 

MMC1_ 

DAT1 

MMC1 

_DAT0 

14 

13 

GND 

PRG0_ 
PRU0_ 

GPO4 

PRG0_ 
PRU0_ 

GPO5 

GND 

PRG0_ 
PRU0_ 

GPO6 

OSPI0 

_CS2# 

GND 

MMC1_ 

DAT3 

MMC1_ 

DAT2 

GND 

13 

12 

PRG0_ 
PRU0_ 

GPO7 

PRG0_ 
PRU0_ 

GPO8 

GND 

PRG0_ 
PRU0_ 

GPO9 

PRG0_ 
PRU0_ 
GPO10 

OSPI0 

_CS3# 

GPMC0 

_CS2# 

GND 

GPMC0 

_CS1# 

GPMC0 

_CS0# 

12 

11 

PRG0_ 
PRU0_ 
GPO11 

GND 

PRG0_ 
PRU0_ 
GPO12 

PRG0_ 
PRU0_ 
GPO13 

GND 

GND 

GPMC0 

_CS3# 

GPMC0 

_ADV# 

_ALE 

GND 

GPMC0 

_CLK 

11 

10 

GND 

PRG0_ 
PRU0_ 
GPO14 

PRG0_ 
PRU0_ 
GPO15 

GND 

PRG0_ 
PRU0_ 
GPO16 

GPMC0 

_BE0# 

_CLE 

GND 

GPMC0 

_AD0 

GPMC0 

_AD1 

GND 

10 

PRG0_ 
PRU0_ 
GPO17 

PRG0_ 
PRU0_ 
GPO18 

GND 

PRG0_ 
PRU0_ 
GPO19 

PRG0_ 
PRU1_ 

GPO0 

GND 

V_ 

1V1 

GND 

 

GND 

V_ 

0V85 

GND 

GPMC0 

_BE1# 

GPMC0 

_AD2 

GND 

GPMC0 

_AD3 

GPMC0 

_AD4 

PRG0_ 
PRU1_ 

GPO1 

GND 

PRG0_ 
PRU1_ 

GPO2 

PRG0_ 
PRU1_ 

GPO3 

GND 

MCU_ 

PORz 

V_ 

1V8 

_AUX 

GND 

GND 

V_ 

1V8A 

GPMC0 

_DIR 

GND 

GPMC0 

_AD5 

GPMC0 

_AD6 

GND 

GPMC0 

_AD7 

GND 

PRG0_ 
PRU1_ 

GPO4 

PRG0_ 
PRU1_ 

GPO5 

GND 

PRG0_ 
PRU1_ 

GPO6 

PORz 
_OUT 

GND 

RFU2 

RFU3 

GND 

GPMC0 

_WP# 

GPMC0 

_OE# 
_RE# 

GND 

GPMC0 

_AD8 

GPMC0 

_AD9 

GND 

PRG0_ 
PRU1_ 

GPO7 

PRG0_ 
PRU1_ 

GPO8 

GND 

PRG0_ 
PRU1_ 

GPO9 

PRG0_ 
PRU1_ 
GPO10 

GND 

RFU1 

V_VDD 
_CORE 

GND 

TQM 

aX4XxL 

_HARD 

_RST# 

GND 

GND 

TQM 

aX4XxL 

_PGOOD 

GND 

TQ_EE 

PROM 

_WC# 

RFU4 

GND 

GPMC0 

_WE# 

GPMC0 

_AD10 

GND 

GPMC0 

_AD11 

GPMC0 

_AD12 

PRG0_ 
PRU1_ 
GPO11 

GND 

PRG0_ 
PRU1_ 
GPO12 

PRG0_ 
PRU1_ 
GPO13 

GND 

PRG1_ 
PRU0_ 

GPO1 

PRG1_ 
PRU0_ 

GPO4 

GND 

PRG1_ 
PRU0_ 
GPO11 

PRG1_ 
PRU0_ 
GPO14 

PRG1_ 
PRU0_ 
GPO18 

PRG1_ 
PRU1_ 

GPO2 

PRG1_ 
PRU1_ 

GPO5 

PRG1_ 
PRU1_ 

GPO9 

GND 

PRG1_ 
PRU1_ 
GPO15 

GPMC0 
_WAIT0 

GND 

GPMC0 

_AD13 

GPMC0 

_AD14 

GND 

GPMC0 

_AD15 

GND 

PRG0_ 
PRU1_ 
GPO14 

PRG0_ 
PRU1_ 
GPO15 

GND 

GND 

PRG1_ 
PRU0_ 

GPO0 

GND 

PRG1_ 
PRU0_ 

GPO7 

PRG1_ 
PRU0_ 
GPO10 

GND 

PRG1_ 
PRU0_ 
GPO17 

PRG1_ 
PRU1_ 

GPO1 

GND 

PRG1_ 
PRU1_ 

GPO8 

PRG1_ 
PRU1_ 
GPO12 

GND 

PRG1_ 
PRU1_ 
GPO18 

GPMC0 
_WAIT1 

GND 

USB0 

_ID 

USB0_ 

DRV 

VBUS 

GND 

PRG0_ 
PRU1_ 
GPO16 

PRG0_ 
PRU1_ 
GPO17 

GND 

PRG0_ 
PRU1_ 
GPO18 

GND 

GND 

PRG1_ 
PRU0_ 

GPO3 

PRG1_ 
PRU0_ 

GPO6 

GND 

PRG1_ 
PRU0_ 
GPO13 

PRG1_ 
PRU0_ 
GPO16 

PRG1_ 
PRU1_ 

GPO0 

PRG1_ 
PRU1_ 

GPO4 

GND 

PRG1_ 
PRU1_ 
GPO11 

PRG1_ 
PRU1_ 
GPO14 

GND 

SERDES 

0_REF 

CLK0_N 

SERDES 

0_REF 

CLK0_P 

GND 

USB0_ 

VBUS 

USB0 

_DM 

PRG0_ 
PRU1_ 
GPO19 

GND 

V_5V 

_IN 

V_5V 

_IN 

GND 

PRG1_ 

MDIO0 
_MDIO 

PRG1_ 
PRU0_ 

GPO2 

GND 

PRG1_ 
PRU0_ 

GPO9 

PRG1_ 
PRU0_ 
GPO12 

GND 

GND 

PRG1_ 
PRU1_ 

GPO3 

PRG1_ 
PRU1_ 

GPO7 

GND 

PRG1_ 
PRU1_ 
GPO13 

PRG1_ 
PRU1_ 
GPO17 

GND 

SERDES 

0_RX_N 

SER 

DES0 

_RX_P 

GND 

USB0 

_DP 

 

V_5V 

_IN 

V_5V 

_IN 

V_5V 

_IN 

GND 

PRG1_ 

MDIO0 

_MDC 

GND 

PRG1_ 
PRU0_ 

GPO5 

PRG1_ 
PRU0_ 

GPO8 

GND 

PRG1_ 
PRU0_ 
GPO15 

PRG1_ 
PRU0_ 
GPO19 

GND 

PRG1_ 
PRU1_ 

GPO6 

PRG1_ 
PRU1_ 
GPO10 

GND 

PRG1_ 
PRU1_ 
GPO16 

PRG1_ 
PRU1_ 
GPO19 

GND 

SER 

DES0 

_TX_N 

SER 

DES0 

_TX_P 

 

 

AA 

AB 

 

 
No pads at corner position A1, A22, AB1 and AB 22 
No pads at center position F10 to F17, G10 to G17, H10 to H17, J7 to J17, K7 to K17, L7 to L17, M7 to M17, N7 to N17, P7 to P17, 

R10 to R17, T10 to T17 and U10 to U17 
 
 
 
 
 
 

Summary of Contents for TQMaX4X Series

Page 1: ...TQMaX4XxL Preliminary User s Manual TQMaX4XxL UM 0001 14 03 2022...

Page 2: ...h 10 3 2 3 Memory 11 3 2 3 1 LPDDR4 SDRAM 11 3 2 3 2 eMMC 11 3 2 3 3 NOR Flash 12 3 2 3 4 EEPROMs 12 3 2 4 Clock supply 12 3 2 5 RTC 13 3 2 6 Secure Element 14 3 2 7 Temperature sensor 14 3 2 8 Interf...

Page 3: ...against external effects 30 5 4 Thermal management 30 5 5 Structural requirements 31 6 SAFETY REQUIREMENTS AND PROTECTIVE REGULATIONS 32 6 1 EMC 32 6 2 ESD 32 6 3 Operational safety and personal secu...

Page 4: ...eMMC 10 Table 6 Selection of the boot device NOR flash 10 Table 7 eMMC Flash modes 11 Table 8 NOR Flash modes 12 Table 9 JTAG signals 15 Table 10 I2C address assignment on the module 16 Table 11 Supp...

Page 5: ...Figure 10 Block diagram SEC 14 Figure 11 Block diagram JTAG 15 Figure 12 Block diagram SerDes 16 Figure 13 Block diagram I2C bus on the TQMaX4XxL 16 Figure 14 Block diagram Reset 17 Figure 15 Block d...

Page 6: ...and trademarks are rightly protected by a third party 1 3 Disclaimer TQ Systems GmbH does not guarantee that the information in this Preliminary User s Manual is up to date correct complete or of good...

Page 7: ...This symbol represents important details or aspects for working with TQ products Command A font with fixed width is used to denote commands file names or menu items 1 7 Handling and ESD tips General...

Page 8: ...e manufacturer s specifications of the components used for example CompactFlash cards are to be taken note of They contain if applicable additional information that must be taken note of for safe and...

Page 9: ...ule based on the TI Sitara family AM64x and AM243x processors with ARM Cortex A53 Cortex R5 and Cortex M4 cores This Preliminary User s Manual describes the hardware of the TQMaX4XxL Rev 010x and refe...

Page 10: ...e 2 Block diagram AM243x Source Texas Instruments All useful AM64x AM243x signals are routed to the TQMaX4XxL pads There are no restrictions for customers using the TQMaX4XxL with respect to an integr...

Page 11: ...P provided by TQ Systems GmbH see also section 4 3 1 System overview 3 1 1 System architecture block diagram Figure 3 Block diagram TQMaX4XxL 3 1 2 Functionality The following key functions are implem...

Page 12: ...AM243x pins can be configured as different function Please take note of the information in the AM64x AM243x data sheets 1 2 concerning the configuration of these pins before integration start up of y...

Page 13: ...Preliminary User s Manual l TQMaX4XxL UM 0001 l 2022 TQ Systems GmbH Page 8 Table 3 AM243x derivatives Source Texas Instruments...

Page 14: ...ded either directly from the memory device or by a peripheral The following figure shows the implementation of boot strapping on the module Figure 4 Block diagram Boot Strapping According to the Refer...

Page 15: ...00 GPMC NOR 1101 PCIe 1110 xSPI 1111 No boot Dev boot 1001 3 2 2 3 Boot device NOR flash Table 6 Selection of the boot device NOR flash Boot configuration pin Setting TQMaX4XxL BOOTMODE9 Reserved fixe...

Page 16: ...8 bit data 8 bit ECC Up to 1600 Mbps 800 MHz 1 GByte 2 GByte Figure 5 Block diagram DDR3L SDRAM connection 3 2 3 2 eMMC An eMMC is available to the TQMaX4XxL as non volatile data memory for programs...

Page 17: ...te Extended SPI SDR TBD TBD 3 2 3 4 EEPROMs I2 C EEPROMs are provided on the TQMaX4XxL for non volatile storage A distinction is made here between Customer data freely accessible TQ manufacturing data...

Page 18: ...n be supplied from the base board via V_RTC_IN V_RTC_IN 2 0 V to 5 5V RTC_INT and RTC_CLKOUT is accessible at the LGA pads RTC_CLKOUT is only activated as soon as the TQMaX4XxL is supplied with V_5V_I...

Page 19: ...e CPU Reference Manual 3 3 2 8 1 Ethernet switch The AM64x AM243x provides an integrated Ethernet switch CPSW3G supporting Up to 2 Ethernet ports o RMII 10 100 o RGMII 10 100 1000 IEEE 1588 2008 Annex...

Page 20: ...AM243x Data Sheet 1 2 3 2 8 4 JTAG The CPU has a JTAG interface that is directly accessible at the LGA pads The following default configuration is provided on the TQMaX4XxL Figure 11 Block diagram JTA...

Page 21: ...manently provided on the TQMaX4XxL The following devices are connected to the module Figure 13 Block diagram I2C bus on the TQMaX4XxL Die folgende Tabelle zeigt die verwendeten Adressen aller I2C Buss...

Page 22: ...as primary function But USB3 1 and PCIe share common SerDes lanes therefore the functionality is not always available In addition the AM64x AM243x offers a non shared USB 2 0 routed to the TQM AM64x A...

Page 23: ...ult the signal is connected to a pullup to 1 8V so only a LOW can trigger a warm reset of the main domain on the module 3 2 9 2 Reset Status Output 3 2 9 2 1 PORz_OUT The PORz_OUT signal serves as sta...

Page 24: ...oltages of the TQMaX4XxL Table 11 Supply voltages Module pin Signal Voltage Current Use V_5V_IN 4 75 V to 5 25 V TBD Input module supply V_3V3 3 28 V to 3 36 V max 100 mA Output V_1V8 1 78 V to 1 82 V...

Page 25: ...o I O pins may be driven by external components until the power up sequence is completed The end of the power up sequence is signaled by a high level of the TQMaX4XxL_PGOOD signal 3 2 11 4 Power modes...

Page 26: ...must be expected when using additional interfaces in parallel TQMa2434L Current consumption Reset TBD mA TQMaX4XxL_HARD_RST LOW Current consumption theoretical worst case Current consumption is lower...

Page 27: ...PRG0_ PRU0_ GPO15 GND PRG0_ PRU0_ GPO16 GPMC0 _BE0 _CLE GND GPMC0 _AD0 GPMC0 _AD1 GND 10 9 PRG0_ PRU0_ GPO17 PRG0_ PRU0_ GPO18 GND PRG0_ PRU0_ GPO19 PRG0_ PRU1_ GPO0 GND V_ 1V1 GND GND V_ 0V85 GND GPM...

Page 28: ...Power Cycle 10k Pullup on TQMaX4XxL 5 0 V 5 F8 MCU_PORz I Cold reset to CPU via MCU_PORz 10k Pullup on TQMaX4XxL 1 8 V P19 MCU_RESETz B12 I MCU Domain warm reset 10k Pullup on TQMaX4XxL R20 RESET_REQz...

Page 29: ...put and internal pulldown other wise left unconnected 1 8 V Y10 GPMC0_AD0 T20 IO AA10 GPMC0_AD1 U21 IO W9 GPMC0_AD2 T18 IO AA9 GPMC0_AD3 U20 IO AB9 GPMC0_AD4 U18 IO W8 GPMC0_AD5 U19 IO Y8 GPMC0_AD6 V2...

Page 30: ...AA19 ADC0_AIN1 F20 I AB20 ADC0_AIN2 E21 I AA20 ADC0_AIN3 D20 I AB21 ADC0_AIN4 G21 I AA22 ADC0_AIN5 F21 I Y22 ADC0_AIN6 F19 I Y21 ADC0_AIN7 E20 I W17 EXTINT C19 I V17 ECAP0_IN_APWM_OUT D18 IO W18 EXT_R...

Page 31: ...G0_PRU0_GPO16 U4 O A9 PRG0_PRU0_GPO17 U1 O B9 PRG0_PRU0_GPO18 V1 O D9 PRG0_PRU0_GPO19 W1 O E9 PRG0_PRU1_GPO0 Y2 O A8 PRG0_PRU1_GPO1 W2 O C8 PRG0_PRU1_GPO2 V3 O D8 PRG0_PRU1_GPO3 T4 O B7 PRG0_PRU1_GPO4...

Page 32: ...17 IO SERDES Reference Clock In put Output Leave unconnected V3 SERDES0_REFCLK0_N W16 IO Y2 SERDES0_RX_P Y16 I SERDES differential Receive Data W2 SERDES0_RX_N Y15 I AA1 SERDES0_TX_P AA17 O SERDES dif...

Page 33: ...tion timing Muxing Clocks Driver strengths When using a different bootloader this data has to be adapted Details can be requested from TQ support More information can be found in the Support Wiki for...

Page 34: ...Preliminary Preliminary User s Manual l TQMaX4XxL UM 0001 l 2022 TQ Systems GmbH Page 29 Figure 19 TQMaX4XxL side view Figure 20 Recommended PCB land pattern for TQMaX4XxL top view through TQMaX4XxL...

Page 35: ...ssipation mainly arises at the processor the switching regulators and the LPDDR4 devices It is the customer s responsibility to define a suitable cooling method for his use case Attention Destruction...

Page 36: ...tening measures If there are high requirements for vibration and shock resistance a module holder must be provided in the final application to additionally hold the module in position Since no heavy a...

Page 37: ...ng measures are recommended for a carrier board Generally applicable Shielding of the inputs shielding connected well to ground housing on both ends Supply voltages Protection by suppressor diode s Sl...

Page 38: ...eries are used on the TQMaX4XxL 6 10 Packaging By environmentally friendly processes production equipment and products we contribute to the protection of our environment To be able to reuse the TQMaX4...

Page 39: ...Scaling EEPROM Electrically Erasable Programmable Read only Memory EMC Electro Magnetic Compatibility eMMC embedded Multi Media Card EN Europ ische Norm ESD Electro Static Discharge EU European Union...

Page 40: ...pacitor REACH Registration Evaluation Authorisation and restriction of Chemicals RF Radio Frequency RFU Reserved for Future Usage RGB Red Green Blue RGMII Reduced Gigabit Media Independent Interface R...

Page 41: ...ments 2 AM243x Sitara Microcontrollers Datasheet B Jul 2021 Texas Instruments 3 AM64x AM243x Processors Silicon Revision 1 0 Technical Reference Manual C Sep 2021 Texas Instruments 4 Errata AM64x AM24...

Page 42: ...TQ Systems GmbH M hlstra e 2 l Gut Delling l 82229 Seefeld Info TQ Group TQ Group...

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