Preliminary Preliminary User's Manual l TQMaX4XxL UM 0001 l © 2022, TQ-Systems GmbH
Page 15
addition, the PRU-ICSSG also enables additional interfaces in the SoC including sigma delta decimation filters and absolute
encoder interfaces.
The signals of the PRUs are available as multiplexing options at the pads of the TQMaX4XxL. The IO logic of the interface is 1.8 V.
3.2.8.3
GPIO
Besides their interface function, most AM64x / AM243x pins can also be used as GPIOs. Details are to be taken from the AM64x /
AM243x Data Sheet (1) (2).
3.2.8.4
JTAG
The CPU has a JTAG interface that is directly accessible at the LGA pads. The following default configuration is provided on the
TQMaX4XxL:
Figure 11:
Block diagram JTAG
The following table shows the signals used by the JTAG interface.
Table 9: JTAG signals
Signal / Multiplexing
I/O
Power domain
Note
TCK
I
VDDSHV_MCU (1,8 V)
4.7 kΩ Pull-up on module
TDI
I
TDO
O
TMS
I
4.7 kΩ Pull-up on module
TRST#
I
4.7 kΩ Pull-up on module
EMU[1:0]
IO
Optional signals, not required for JTAG
3.2.8.5
SerDes
The CPU has a SerDes lane, which can be used either as PCIe or USB3.0. The signals are directly accessible at the LGA pads.
For more information please refer to the Reference Manual (3).
