User's Manual l TQMaRZG2x UM 0100 l © 2021, TQ-Systems GmbH
Page 14
3.3.2
Memory
3.3.2.1
SDRAM
Up to 8 Gbyte of LPDDR4-3200 SDRAM can be assembled on the TQMaRZG2x, optional with In-Line ECC:
•
TQMaRZG2H, TQMaRZG2M:
8 Gbyte
•
TQMaRZG2N:
4 Gbyte
3.3.2.2
eMMC
The RZ/G2x provides an SDHC interface, which is connected to SDHI3.
The eMMC on the TQMaRZG2x is configured as MLC by default, but it can be configured as SLC (higher reliability, half capacity).
Please contact
for details.
In case the eMMC is not populated on the TQMaRZG2x, a 1.8 V eMMC can be connected on the carrier board.
RZ/G2x
SD3_CLK
Connector
NP
eMMC
NP
NP
NP
CLK
CMD
DS
DAT[7:0]
RST#
SD3_CMD
SD3_DS
SD3_DAT[7:0]
PRESET#
Figure 6:
Block diagram eMMC interface
The TQMaRZG2x supports the following transfer modes:
Table 9:
eMMC transfer modes
Mode
1-bit
4-bit
8-bit
Remark
Default Speed
–
–
–
–
High Speed
–
–
Yes
Boot process
HS200
–
–
Yes
U-Boot
HS400
–
–
Yes
Linux
3.3.2.3
QSPI NOR
The TQMaRZG2x provides two QSPI interfaces, QSPI0 and QSPI1, which operate at 1.8 V.
The TQMaRZG2x supports three different configurations.
1.
No NOR flash assembled on the TQMaRZG2x, both QSPI interfaces are available at the TQMaRZG2x connectors
2.
1 × QSPI NOR flash assembled on the TQMaRZG2x
3.
2 × QSPI NOR flash assembled on the TQMaRZG2x