TQ TQMaRZG2x, User Manual

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User's Manual l TQMaRZG2x UM 0100 l © 2021, TQ-Systems GmbH Page 9
3.1.4 Pinout TQMaRZG2x (continued)
Table 5: Pinout connector X2 (continued)
Dir. Level Group Signal X2 Signal Group Level Dir.
IO 3.3 V SSI SSI_SDATA8 A56 B56 AUDIO_CLKA_A ADG 3.3 V I
IO 3.3 V SSI SSI_SDATA7 A57 B57 DGND Ground 0 V –
IO 3.3 V SSI SSI_SDATA6 A58 B58 SSI_SCK5 SSI 3.3 V IO
IO 3.3 V SSI SSI_SDATA5 A59 B59 DGND Ground 0 V –
– 0 V Ground DGND A60 B60 DGND Ground 0 V –
IO 3.3 V SSI SSI_SDATA4 A61 B61 SSI_SCK6 SSI 3.3 V IO
IO 3.3 V SSI SSI_SDATA3 A62 B62 DGND Ground 0 V –
IO 3.3 V SSI SSI_SDATA2_A A63 B63 SSI_SCK78 SSI 3.3 V IO
IO 3.3 V SSI SSI_SDATA1_A A64 B64 DGND Ground 0 V –
IO 3.3 V SSI SSI_SDATA0 A65 B65 SSI_SCK4 SSI 3.3 V IO
IO 3.3 V SSI SSI_WS78 A66 B66 DGND Ground 0 V –
IO 3.3 V SSI SSI_WS5 A67 B67 SSI_SCK349 SSI 3.3 V IO
IO 3.3 V SSI SSI_WS6 A68 B68 DGND Ground 0 V –
IO 3.3 V SSI SSI_WS4 A69 B69 SSI_SCK01239 SSI 3.3 V IO
– 0 V Ground DGND A70 B70 DGND Ground 0 V –
IO 3.3 V SSI SSI_WS349 A71 B71 VDDQVA_SD0 SD 1.8 / 3.3 V I
IO 3.3 V SSI SSI_WS01239 A72 B72 VDDQVA_SD1 SD 1.8 / 3.3 V I
O 3.3 V TEMP EVENT_TEMPSENSOR# A73 B73 VDDQVA_SD2 SD 1.8 / 3.3 V I
I 3.3 V EEPROM EEPROM_WP A74 B74 VDDQVA_SD3 SD 1.8 / 3.3 V I
O 3.3 V SCIF TX0 A75 B75 DGND Ground 0 V –
I 3.3 V SCIF RX0 A76 B76 SCK2 SCIF 3.3 V O
IO 3.3 V SCIF CTS0# A77 B77 DGND Ground 0 V –
IO 3.3 V SCIF RTS0# A78 B78 TX2_A SCIF 3.3 V O
O 3.3 V SCIF SCK0 A79 B79 RX2_A SCIF 3.3 V I
– 0 V Ground DGND A80 B80 DGND Ground 0 V –
O 3.3 V SCIF TX1_A A81 B81 MLB_CLK MLB 3.3 V I
I 3.3 V SCIF RX1_A A82 B82 MLB_DAT MLB 3.3 V IO
IO 3.3 V SCIF CTS1# A83 B83 MLB_SIG MLB 3.3 V IO
IO 3.3 V SCIF RTS1# A84 B84 HRTS0# HSCIF 3.3 V IO
IO 3.3 V MSIOF MSIOF0_SYNC A85 B85 HCTS0# HSCIF 3.3 V IO
O 3.3 V MSIOF MSIOF0_TXD A86 B86 HRX0 HSCIF 3.3 V I
I 3.3 V MSIOF MSIOF0_RXD A87 B87 HTX0 HSCIF 3.3 V O
O 3.3 V MSIOF MSIOF0_SS1 A88 B88 DGND Ground 0 V –
O 3.3 V MSIOF MSIOF0_SS2 A89 B89 HSCK0 HSCIF 3.3 V I
– 0 V Ground DGND A90 B90 DGND Ground 0 V –
O 3.3 V MSIOF MSIOF0_SCK A91 B91 SD1_DAT0 SD 1.8 / 3.3 V IO
– 0 V Ground DGND A92 B92 SD1_DAT1 SD 1.8 / 3.3 V IO
I 3.3 V SD SD0_WP A93 B93 SD1_DAT2 SD 1.8 / 3.3 V IO
I 3.3 V SD SD0_CD A94 B94 SD1_DAT3 SD 1.8 / 3.3 V IO
IO 1.8 / 3.3 V SD SD0_CMD A95 B95 SD1_CD SD 3.3 V I
IO 1.8 / 3.3 V SD SD0_DAT0 A96 B96 SD1_WP SD 3.3 V I
IO 1.8 / 3.3 V SD SD0_DAT1 A97 B97 SD1_CMD SD 1.8 / 3.3 V IO
IO 1.8 / 3.3 V SD SD0_DAT2 A98 B98 DGND Ground 0 V –
IO 1.8 / 3.3 V SD SD0_DAT3 A99 B99 SD1_CLK SD 1.8 / 3.3 V O
– 0 V Ground DGND A100 B100 DGND Ground 0 V –
O 1.8 / 3.3 V SD SD0_CLK A101 B101 DGND Ground 0 V –
– 0 V Ground DGND A102 B102 SD2_DAT0 SD 1.8 / 3.3 V IO
I 3.3 V SECURE SE_ENABLE A103 B103 SD2_DAT1 SD 1.8 / 3.3 V IO
IO 3.3 V SECURE SE_7816_IO1 A104 B104 SD2_DAT2 SD 1.8 / 3.3 V IO
IO 3.3 V SECURE SE_7816_IO2 A105 B105 SD2_DAT3 SD 1.8 / 3.3 V IO
I 3.3 V SECURE SE_7816_RST# A106 B106 SD2_CMD SD 1.8 / 3.3 V IO
IO 3.3 V SECURE SE_14443_LA A107 B107 SD2_DS SD 1.8 / 3.3 V I
IO 3.3 V SECURE SE_14443_LB A108 B108 DGND Ground 0 V –
O 3.3 V SECURE SE_7816_CLK A109 B109 SD2_CLK SD 1.8 / 3.3 V O
– 0 V Ground DGND A110 B110 DGND Ground 0 V –