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3.2.5.16

External clock sources

The i.MX 8M Mini has the option to use two external oscillators as clock sources.
All four CPU balls provided for this purpose are connected to TQMa8MxML LGA pads.
The following table shows these clock signals.

Table 34: XTAL signals

Signal

CPU ball

TQMa8MxML

Power group

CLK1_IN

H27

W16

V_1V8

CLK1_OUT

H26

W17

CLK2_IN

J27

W15

CLK2_OUT

J26

V16

3.2.6

Unspecific signals

The following table lists all signals that are not assigned to a specific group.

Table 35:

Unspecific signals

Signal

Direction

CPU ball

TQMa8MxML

Power group

PMIC_WDOG#

AG13

V_3V3

M4_NMI / M7_NMI

AF12

ONOFF

A25

V_1V8_SNVS

TEST_MODE

D26

E11

V_3V3

11:

M4_NMI on the TQMa8MxML, M7_NMI on the TQMa8MxNL.

12:

Signal is only available on the TQMa8MxML.

Summary of Contents for TQMa8MxML

Page 1: ...TQMa8MxML TQMa8MxNL User s Manual TQMa8MxML UM 0103 04 07 2022...

Page 2: ...i MX 8M Mini derivatives 19 3 2 1 2 i MX 8M Nano derivatives 19 3 2 1 3 i MX 8M Mini i MX 8M Nano main differences 19 3 2 1 4 i MX 8M Mini errata 19 3 2 1 5 Boot Modes 20 3 2 1 6 Boot configuration i...

Page 3: ...2 9 8 Standby and SNVS 46 3 2 9 9 PMIC 47 3 2 10 Impedances 48 4 SOFTWARE 48 5 MECHANICS 49 5 1 Dimensions 49 5 2 Component placement 50 5 3 Adaptation to the environment 51 5 4 Protection against ex...

Page 4: ...a8MxNL 23 Table 17 Trust Secure Element signals 25 Table 18 Internal interfaces 27 Table 19 ENET signals in RGMII mode 27 Table 20 GPIO signals 28 Table 21 I2 C signals 29 Table 22 Address assignment...

Page 5: ...ock diagram JTAG interface 30 Figure 12 Block diagram MIPI CSI 31 Figure 13 Block diagram MIPI DSI 32 Figure 14 Block diagram PCIe 33 Figure 15 Block diagram SAI1 34 Figure 16 Block diagram SPDIF 36 F...

Page 6: ...0101 04 05 2021 Petz All 3 2 5 15 Table 37 Non functional changes expressions formatting Information regarding pull ups added Values added 0102 27 10 2021 Kreuzer Table 37 Values added 0104 01 07 202...

Page 7: ...trademarks are rightly protected by a third party 1 3 Disclaimer TQ Systems GmbH does not guarantee that the information in this User s Manual is up to date correct complete or of good quality Nor do...

Page 8: ...nt details or aspects for working with TQ products Command A font with fixed width is used to denote commands contents file names or menu items 1 7 Handling and ESD tips General handling of your TQ pr...

Page 9: ...of the components used for example CompactFlash cards are to be taken note of They contain if applicable additional information that must be taken note of for safe and reliable operation These docume...

Page 10: ...ems GmbH product range and offers an outstanding computing performance All essential i MX 8M Mini pins are routed to the TQMa8MxML LGA pads There are therefore no restrictions for customers using the...

Page 11: ...User s Manual l TQMa8MxML UM 0103 l 2022 TQ Systems GmbH Page 5 2 2 CPU block diagrams Figure 1 Block diagram i MX 8M Mini Source NXP Figure 2 Block diagram i MX 8M Nano Source NXP...

Page 12: ...Mx The pin assignment in Table 5 refers to a TQMa8MxNL with i MX 8M Nano Quad CPU in combination with the Starterkit MBa8Mx A certain i MX 8M Mini or i MX 8M Nano derivative listed in Table 7 and Tabl...

Page 13: ...13 12 SAI3_M CLK SAI3_R XD I2C3_S DA GND TEMP_E VENT ISO_78 16_RST GPIO3_I O14 QSPI_A _SCLK GND V_ENET 12 11 GND SAI3_R XFS GND I2C2_S CL TEST_M ODE GND GPIO2_I O00 GND GPIO2_I O11 GND 11 10 SAI3_R XC...

Page 14: ...I1_MOSI ECSPI O V_ECSPI B18 D6 ECSPI1_SCLK ECSPI O V_ECSPI A17 B6 ECSPI1_SS0 ECSPI O V_ECSPI B16 A8 ECSPI2_MISO ECSPI I V_ECSPI C19 B8 ECSPI2_MOSI ECSPI O V_ECSPI D19 E6 ECSPI2_SCLK ECSPI O V_ECSPI B1...

Page 15: ...O I O 1 8 V T8 U26 GPIO2_IO07 GPIO I O 1 8 V W13 W27 GPIO2_IO08 GPIO I O 1 8 V W10 W26 GPIO2_IO09 GPIO I O 1 8 V V13 R23 GPIO2_IO10 GPIO I O 1 8 V V14 R24 GPIO2_IO11 GPIO I O 1 8 V V11 R22 GPIO3_IO14...

Page 16: ...8 3 3 V B15 A16 CSI_CLK_N MIPI_CSI I 1 8 V L17 B16 CSI_CLK_P MIPI_CSI I 1 8 V M17 A14 CSI_D0_N MIPI_CSI I 1 8 V J19 B14 CSI_D0_P MIPI_CSI I 1 8 V K19 A15 CSI_D1_N MIPI_CSI I 1 8 V K18 B15 CSI_D1_P MI...

Page 17: ...I O 3 3 V M2 AF21 SAI1_TXD3 SAI O 3 3 V M3 AG22 SAI1_TXD4 SAI O 3 3 V N2 AF22 SAI1_TXD5 SAI O 3 3 V N4 AG23 SAI1_TXD6 SAI O 3 3 V P4 AF23 SAI1_TXD7 SAI O 3 3 V P3 AB19 SAI1_TXFS SAI O 3 3 V L4 AD19 SA...

Page 18: ...D O 1 8 3 3 V T7 AA27 SD2_WP SD I 1 8 3 3 V R6 A25 ONOFF SNVS I 1 8 V G7 AF8 SPDIF_EXT_CLK SPDIF I 3 3 V D8 AG9 SPDIF_RX SPDIF I 3 3 V F8 AF9 SPDIF_TX SPDIF O 3 3 V E9 D26 TEST_MODE TEST I 3 3 V E11 E...

Page 19: ...16_IO2 GND GPIO2_I O02 GPIO2_I O09 GPIO2_I O07 13 12 SAI3_M CLK SAI3_R XD I2C3_S DA GND TEMP_E VENT ISO_78 16_RST GPIO3_I O14 QSPI_A _SCLK GND V_ENET 12 11 GND SAI3_R XFS GND I2C2_S CL BOOT_ MODE3 GND...

Page 20: ...SO ECSPI I V_ECSPI C19 B8 ECSPI2_MOSI ECSPI O V_ECSPI D19 E6 ECSPI2_SCLK ECSPI O V_ECSPI B19 A6 ECSPI2_SS0 ECSPI O V_ECSPI C17 AC27 ENET_MDC ENET O V_ENET V6 AB27 ENET_MDIO ENET I O V_ENET U6 AE27 ENE...

Page 21: ...O10 GPIO I O 1 8 V V14 R24 GPIO2_IO11 GPIO I O 1 8 V V11 R22 GPIO3_IO14 GPIO I O 1 8 V T12 ISO_7816_CLK ISO_7816 I 3 3 V F15 ISO_7816_IO1 ISO_7816 I O 3 3 V F14 ISO_7816_IO2 ISO_7816 I O 3 3 V F13 ISO...

Page 22: ...5 J12 V_UART Power Pin 1 8 3 3 V B15 P23 QSPI_A_DATA0 QSPI I O 1 8 V V10 K24 QSPI_A_DATA1 QSPI I O 1 8 V U9 K23 QSPI_A_DATA2 QSPI I O 1 8 V V9 N23 QSPI_A_DATA3 QSPI I O 1 8 V W9 N22 QSPI_A_SCLK QSPI O...

Page 23: ...1 8 3 3 V T7 AA27 SD2_WP SD I 1 8 3 3 V R6 A25 ONOFF SNVS I 1 8 V G7 AF8 SPDIF_EXT_CLK SPDIF I 3 3 V D8 AG9 SPDIF_RX SPDIF I 3 3 V F8 AF9 SPDIF_TX SPDIF O 3 3 V E9 E14 UART1_RXD UART I V_UART E16 F13...

Page 24: ...0 P19 PCIE_TXN NC B20 R19 PCIE_TXP NC AB18 K1 SAI1_MCLK NC AF16 F1 SAI1_RXC NC AG15 G1 SAI1_RXD0 NC AF15 G2 SAI1_RXD1 NC AG17 H1 SAI1_RXD2 NC AF17 H3 SAI1_RXD3 NC AG18 H4 SAI1_RXD4 NC AF18 J2 SAI1_RXD...

Page 25: ...derivatives TQMa8MxNL version i MX 8M Nano derivative i MX 8M Nano clock Temperature range TQMa8MSNL XX i MX 8M Nano Solo A53 1 4 GHz M7 600 MHz 40 C 105 C TQMa8MSNLL XX i MX 8M Nano SoloLite A53 1 4...

Page 26: ...ble before the release of IMX_POR It is strongly recommended to use V_3V3 as pull up voltage to ensure a reliable boot behaviour The recommended settings of the config pins for the respective interfac...

Page 27: ...M2 BOOT_CFG9 SAI1_TXD1 L3 Power Cycle Enable 0 No power cycle 1 Enabled BOOT_CFG7 SAI1_RXD7 K4 Boot Speed 0 Normal Regular Boot 1 Fast Boot BOOT_CFG6 SAI1_RXD6 J3 Bus Width 000 1 bit 001 4 bit 010 8...

Page 28: ...7 K4 Boot Speed 0 Normal Regular Boot 1 Fast Boot BOOT_CFG4 SAI1_RXD4 H4 Bus Width 0 1 bit 1 4 bit BOOT_CFG3 SAI1_RXD3 H3 Speed Selection 000 Normal SDR12 001 High SDR25 010 SDR50 011 SDR104 101 Reser...

Page 29: ...m eCSPI not supported 1 0 0 0 Reserved 1 0 0 1 Booting from USDHC1 is only possible on the i MX 8M Nano after burning the fuses and is therefore not used DCD is not supported by the i MX 8M Nano 3 2 2...

Page 30: ...i i MX 8M Mini Nano EEPROM I2C1_SCL I2C1_SDA SCL SDA Figure 5 Block diagram EEPROM interface A 64 Kbit EEPROM 24LC64T is assembled by default on the TQMa8MxML The EEPROM has I2 C address 0x57 101 0111...

Page 31: ...he sensor for ISO 7816 must be connected on the carrier board The following TQMa8MxML signals are used to provide the smartcard interfaces Table 17 Trust Secure Element signals Signal ISO signal name...

Page 32: ...M Mini internal RTC the TQMa8MxML provides a discrete RTC PCF85063A which is connected to I2C1 The quartz used to clock the RTC has a standard frequency tolerance of 20 ppm 25 C The discrete RTC has a...

Page 33: ...ed as interfaces with RGMII being used for standard multiplexing The supply voltage must be set externally to 1 8 V 2 5 V or 3 3 V via LGA pad V_ENET RMII is supported at 1 8 V and 3 3 V RGMII at 1 8...

Page 34: ...signals Signal CPU ball TQMa8MxML Power group GPIO1_IO00 AG14 P6 V_3V3 GPIO1_IO01 AF14 N6 GPIO1_IO03 AF13 N5 GPIO1_IO06 AG11 M6 GPIO1_IO07 AF11 M5 GPIO1_IO09 AF10 L5 GPIO2_IO00 V26 T11 V_1V8 GPIO2_IO...

Page 35: ...faces Table 21 I2 C signals Signal Direction CPU ball TQMa8MxML Power group Remark I2C1_SCL O E9 C10 V_3V3 4 7 k PU to 3 3 V on TQMa8MxML I2C1_SDA I O F9 C9 4 7 k PU to 3 3 V on TQMa8MxML I2C2_SCL O D...

Page 36: ...this signal to enable the setting of the different Boot Modes i MX 8M Mini Nano LGA JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TDO JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST JTAG_TRST JTAG_MOD GND Figure 11...

Page 37: ...MX 8M Mini Nano LGA CSI_CLK_N P CSI_D 3 0 _N P MIPI_CSI_CLK_N P MIPI_CSI_D 3 0 _N P Figure 12 Block diagram MIPI CSI The following table shows the signals used by the MIPI CSI interface Table 24 MIPI...

Page 38: ...GA DSI_D 3 0 _N P DSI_CLK_N P MIPI_DSI_D 3 0 _N P MIPI_DSI_CLK_N P MIPI_VREG_CAP GND Figure 13 Block diagram MIPI DSI The following table shows the signals used by the MIPI DSI interface Table 25 MIPI...

Page 39: ...dard must be provided on the carrier board i MX 8M Mini LGA PCIE_TXN P PCIE_RXN P PCIE_TXN P PCIE_RXN P PCIE_RESREF PCIE_REF_CLKN P PCIE_REF_CLKN P GND Figure 14 Block diagram PCIe The following table...

Page 40: ...k to Ground are recommended Clock pins can be used as input or output i MX 8M Mini LGA SAI1_TXC SAI1_TXFS SAI1_RXC SAI1_TXD 7 0 SAI1_TXC SAI1_TXFS SAI1_TXD 7 0 SAI1_RXC SAI1_RXFS SAI1_RXFS SAI1_RXD 7...

Page 41: ...18 K2 NC SAI1_TXD0 O AG20 L1 NC SAI1_TXD1 O AF20 L3 NC SAI1_TXD2 O AG21 M2 NC SAI1_TXD3 O AF21 M3 NC SAI1_TXD4 O AG22 N2 NC SAI1_TXD5 O AF22 N4 NC SAI1_TXD6 O AG23 P4 NC SAI1_TXD7 O AF23 P3 NC SAI1_TX...

Page 42: ...o the TQMa8MxML LGA pads i MX 8M Mini Nano LGA SPDIF_RX SPDIF_TX SPDIF_RX SPDIF_TX SPDIF_EXT_CLK SPDIF_EXT_CLK Figure 16 Block diagram SPDIF The following table shows the signals used by the SPDIF int...

Page 43: ...8 V or 3 3 V via LGA pad V_ECSPI i MX 8M Mini Nano LGA ECSPI1_SS0 ECSPI1_MOSI ECSPI1_SCLK ECSPI1_MISO ECSPI1 Interface ECSPI2_SS0 ECSPI2 Interface ECSPI2_MOSI ECSPI2_MISO ECSPI2_SCLK Figure 17 Block...

Page 44: ...ltage supply must be set to 1 8 V or 3 3 V via LGA pad V_UART i MX 8M Mini Nano LGA UART 4 1 _RXD UART 4 1 _TXD UART 4 1 _RX UART 4 1 _TX Figure 18 Block diagram UART interfaces The following table sh...

Page 45: ...ted with 10 k When using USB OTG it is recommended to use the OTG_ID signal instead of the regular ID signal The regular ID signal is available as placement option i MX 8M Mini LGA USB2_ID USB2_VBUS U...

Page 46: ...ni Nano LGA SD2_CLK SD2_CMD SD2_CLK SD2_CMD SD2_DATA 3 0 SD2_CD SD2_DATA 3 0 SD2_CD GPIO1_IO04 PMIC PCA9450 SD_VSEL SD2_WP SD2_WP SD2_RST SD2_RESET NVCC_SD2 LDO SW_EN SWOUT V_3V3_SD Figure 20 Block di...

Page 47: ...4 XTAL signals Signal CPU ball TQMa8MxML Power group CLK1_IN H27 W16 V_1V8 CLK1_OUT H26 W17 CLK2_IN J27 W15 CLK2_OUT J26 V16 3 2 6 Unspecific signals The following table lists all signals that are not...

Page 48: ..._RESET Figure 21 Block diagram Reset The following table describes the reset signals available at the TQMa8MxML LGA pads Table 36 Reset signals Signal Direction TQMa8MxML Power group Remark RESET_IN I...

Page 49: ...r Boot_Mode pins while that of the i MX 8M Mini is set using only two In addition to BOOT_MODE0 and BOOT_MODE1 JTAG_TRST is used as BOOT_MODE2 and TEST_MODE as BOOT_MODE3 on the TQMa8MxNL 3 2 8 4 SAI...

Page 50: ...seen as an approximate value The power consumption strongly depends on the application the mode of operation and the operating system For more information on power consumption and savings options see...

Page 51: ...board V_LICELL A coin cell can be connected to the TQMa8MxML LGA pad D15 V_LICELL to supply the optional discrete RTC See chapter 3 2 4 2 for information on the LICELL or RTC options Note RTC power su...

Page 52: ...nerated on the TQMa8MxML there are timing requirements for the carrier board design with respect to the voltages generated on the carrier board After power up of the 5V supply for the TQMa8MxML the PM...

Page 53: ...rface The PMIC has I2 C address 0x25 010 0101b The following PMIC and power management signals are available on the TQMa8MxML LGA pads Table 40 PMIC signals Signal Direction TQMa8MxML Power group Rema...

Page 54: ...ls 90 differential 90 10 differential Differential MIPI signals CSI and DSI 100 differential 100 10 differential Differential RGMII signals 100 differential 100 10 differential 4 SOFTWARE The TQMa8MxM...

Page 55: ...heights Dim Value Tolerance Remark A 0 125 mm 0 075 mm TQMa8MxML LGA pads height 0 025 mm B 1 6 mm 0 16 mm PCB without solder resist C 1 25 mm 0 11 mm Height CPU soldered C1 1 22 mm 0 05 mm Highest co...

Page 56: ...lacement Figure 28 TQMa8MxML component placement top The labels on the TQMa8MxML show the following information Table 43 Labels on TQMa8MxML Label Content AK1 TQMa8MxML version and revision AK2 Serial...

Page 57: ...ication See NXP documents 6 and 10 for further information Attention Destruction or malfunction TQMa8MxML cooling The i MX 8M Mini belongs to a performance category in which a cooling system is essent...

Page 58: ...g of all signals which can be connected externally also slow signals and DC can radiate RF indirectly Direct signal routing without stubs 6 2 ESD In order to avoid interspersion on the signal path fro...

Page 59: ...alfunction TQMa8MxML cooling The i MX 8M Mini belongs to a performance category in which a cooling system is essential It is the user s sole responsibility to define a suitable heat sink weight and mo...

Page 60: ...nts on the TQMa8MxML 7 5 Battery No batteries are assembled on the TQMa8MxML 7 6 Packaging The TQMa8MxML is delivered in reusable packaging 7 7 Other entries By environmentally friendly processes prod...

Page 61: ...EPROM Electrically Erasable Programmable Read Only Memory EMC Electromagnetic Compatibility eMMC embedded Multimedia Card Flash EN Europ ische Norm European standard ESD Electrostatic Discharge EuP En...

Page 62: ...riction of Chemicals RF Radio Frequency RGMII Reduced Gigabit Media Independent Interface RMII Reduced Media Independent Interface RoHS Restriction of the use of certain Hazardous Substances ROM Read...

Page 63: ...heet for Industrial Products Rev 3 Apr 2022 NXP 5 i MX 8M Mini Hardware Developer s Guide Rev 3 0 Dec 2021 NXP 6 i MX 8M Nano Hardware Developer s Guide Rev 2 Nov 2021 NXP 7 PMIC PCA9450 Data Sheet Re...

Page 64: ...TQ Systems GmbH M hlstra e 2 l Gut Delling l 82229 Seefeld Info TQ Group TQ Group...

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