TQ TQMa8MxML, User Manual

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User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 14
3.1.1.4 TQMa8MxNL signals
Details about the electrical characteristics of single pins and interfaces are to be taken from the i.MX 8M Nano documentation
(2), (4), (6), as well as the PMIC Data Sheet (7).
Table 5: TQMa8MxNL, signals
CPU ball Signal Group Dir. Level TQMa8MxNL pad
G26 BOOT_MODE0 Boot_Mode I 3.3 V F9
G27 BOOT_MODE1 Boot_Mode I 3.3 V F10
C27 BOOT_MODE2 Boot_Mode I 3.3 V T16
D26 BOOT_MODE3 Boot_Mode I 3.3 V E11
H27 CLK1_IN CLK I 1.8 V W16
H26 CLK1_OUT CLK O 1.8 V W17
J27 CLK2_IN CLK I 1.8 V W15
J26 CLK2_OUT CLK O 1.8 V V16
A7 ECSPI1_MISO ECSPI I V_ECSPI A18
B7 ECSPI1_MOSI ECSPI O V_ECSPI B18
D6 ECSPI1_SCLK ECSPI O V_ECSPI A17
B6 ECSPI1_SS0 ECSPI O V_ECSPI B16
A8 ECSPI2_MISO ECSPI I V_ECSPI C19
B8 ECSPI2_MOSI ECSPI O V_ECSPI D19
E6 ECSPI2_SCLK ECSPI O V_ECSPI B19
A6 ECSPI2_SS0 ECSPI O V_ECSPI C17
AC27 ENET_MDC ENET O V_ENET V6
AB27 ENET_MDIO ENET I/O V_ENET U6
AE27 ENET_RD0 ENET I V_ENET V3
AD27 ENET_RD1 ENET I V_ENET V4
AD26 ENET_RD2 ENET I V_ENET W5
AC26 ENET_RD3 ENET I V_ENET W6
AF27 ENET_RX_CTL ENET I V_ENET W2
AE26 ENET_RXC ENET I V_ENET W3
AG26 ENET_TD0 ENET O V_ENET V1
AF26 ENET_TD1 ENET O V_ENET U2
AG25 ENET_TD2 ENET O V_ENET U1
AF25 ENET_TD3 ENET O V_ENET T2
AF24 ENET_TX_CTL ENET O V_ENET R2
AG24 ENET_TXC ENET O V_ENET T1
– RTC_EVENT# Event O OD 5 E14
– TEMP_EVENT# Event O OD 5 E12
E9 I2C1_SCL I2C O 3.3 V C10
F9 I2C1_SDA I2C I/O 3.3 V C9
D10 I2C2_SCL I2C O 3.3 V D11
D9 I2C2_SDA I2C I/O 3.3 V D10
E10 I2C3_SCL I2C O 3.3 V C13
F10 I2C3_SDA I2C I/O 3.3 V C12
D13 I2C4_SCL I2C O 3.3 V C14
E13 I2C4_SDA I2C I/O 3.3 V D13
AF12 M7_NMI NMI I 3.3 V K5
AG13 PMIC_WDOG# WDOG O 3.3 V K6
5: Requires PU to 3.3 V.