User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH
Page 23
3.2.1.7
Boot configuration i.MX 8M Nano
The i.MX 8M Nano uses four signals to select the boot source. The signals JTAG_TRST# and TEST_MODE are additionally used.
To use these pins as boot selection pins, they require a pull-up/pull-down wiring to 3.3 V or Ground.
It is strongly recommended to use V_3V3 as pull-up voltage to ensure a reliable boot behaviour.
Table 15:
Boot configuration i.MX 8M Nano
Boot source
BOOT_MODE3
BOOT_MODE2
BOOT_MODE1
BOOT_MODE0
Boot from eFuse
0
0
0
0
Serial Downloader (USB OTG1)
0
0
0
1
Boot from USDHC3 (eMMC)
0
0
1
0
Boot from USDHC2 (SD card)
0
0
1
1
Boot from NAND (not supported)
0
1
0
x
Boot from QSPI (3 Byte Read)
0
1
1
0
Boot from QSPI (Hyperflash)
0
1
1
1
Boot from eCSPI (not supported)
1
0
0
0
(Reserved)
1
0
0
1
Booting from USDHC1 is only possible on the i.MX 8M Nano after burning the fuses and is therefore not used. DCD is not
supported by the i.MX 8M Nano.
3.2.2
Memory
3.2.2.1
LPDDR4 SDRAM
An LPDDR4 SDRAM chip is assembled on the TQMa8MxML or TQMa8MxNL.
The following table shows details of the SDRAM assembled:
Table 16:
LPDDR4 SDRAM on TQMa8MxML or TQMa8MxNL
Module
Interface width
Max. size
JEDEC standard
I/O clock
TQMa8MxML
32 bit
4 Gbyte
LPDDR4-3000
1500 MHz
TQMa8MxNL
16 bit
2 Gbyte
LPDDR4-3200
1600 MHz
3.2.2.2
eMMC NAND Flash
An eMMC NAND Flash is provided on the TQMa8MxML for boot loader and application software.
The eMMC is connected to the i.MX 8M Mini via USDHC3.
The i.MX 8M Mini and i.MX 8M Nano support transfer modes up to the current eMMC standard v5.1 according to JESD84-B51.
In DDR mode (HS400) data rates of up to 400 Mbyte/s can be achieved.
The boot configuration is described in chapter 3.2.1.5
