TQ TQMa8MxML, User Manual

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User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 12
3.1.1.2 TQMa8MxML signals (continued)
Table 3: TQMa8MxML, signals (continued)
CPU ball Signal Group Dir. Level TQMa8MxML pad
P23 QSPI_A_DATA0 QSPI I/O 1.8 V V10
K24 QSPI_A_DATA1 QSPI I/O 1.8 V U9
K23 QSPI_A_DATA2 QSPI I/O 1.8 V V9
N23 QSPI_A_DATA3 QSPI I/O 1.8 V W9
N22 QSPI_A_SCLK QSPI O 1.8 V U12
N24 QSPI_A_SS0# QSPI O 1.8 V U10
– PMIC_RST# Reset I 1.8 V E6
– RESET_IN# Reset I OD 4 E7
– RESET_OUT# Reset O OD
4
F7
AA26 SD2_CD# SD I 1.8 / 3.3 V P5
W23 SD2_CLK SD O 1.8 / 3.3 V U5
W24 SD2_CMD SD I/O 1.8 / 3.3 V T5
AB23 SD2_DATA0 SD I/O 1.8 / 3.3 V U3
AB24 SD2_DATA1 SD I/O 1.8 / 3.3 V T4
V24 SD2_DATA2 SD I/O 1.8 / 3.3 V R3
V23 SD2_DATA3 SD I/O 1.8 / 3.3 V R4
AB26 SD2_RST# SD O 1.8 / 3.3 V T7
AA27 SD2_WP SD I 1.8 / 3.3 V R6
A25 ONOFF SNVS I 1.8 V G7
AF8 SPDIF_EXT_CLK SPDIF I 3.3 V D8
AG9 SPDIF_RX SPDIF I 3.3 V F8
AF9 SPDIF_TX SPDIF O 3.3 V E9
D26 TEST_MODE TEST I 3.3 V E11
E14 UART1_RXD UART I V_UART E16
F13 UART1_TXD UART O V_UART D16
F15 UART2_RXD UART I V_UART G16
E15 UART2_TXD UART O V_UART F16
E18 UART3_RXD UART I V_UART J16
D18 UART3_TXD UART O V_UART H16
F19 UART4_RXD UART I V_UART L16
F18 UART4_TXD UART O V_UART K16
A22 USB1_DN USB I/O 3.3 V U19
B22 USB1_DP USB I/O 3.3 V V19
D22 USB1_ID USB I 1.8 V N16
F22 USB1_VBUS USB P 5 V P16
AD10 USB1_OTG_ID USB I 3.3 V J5
AD9 USB1_OTG_OC USB I 3.3 V H6
AB10 USB1_OTG_PWR USB O 3.3 V H5
A23 USB2_DN USB I/O 3.3 V V18
B23 USB2_DP USB I/O 3.3 V W18
D23 USB2_ID USB I 1.8 V P17
F23 USB2_VBUS USB P 5 V R17
AC10 USB2_OTG_ID USB I 3.3 V J6
AB9 USB2_OTG_OC USB I 3.3 V G6
AC9 USB2_OTG_PWR USB O 3.3 V G5
4: Requires PU to 1.8 V, max. 3.6 V.