TQ TQMa8MxML, User Manual

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User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 10
3.1.1.2 TQMa8MxML signals (continued)
Table 3: TQMa8MxML, signals (continued)
CPU ball Signal Group Dir. Level TQMa8MxML pad
– GND
A5, A8, A11, A14, A16, B2, B5, B7, B10, B17, C5, C6, C8, C11, C15, C16, C18, D3, D4,
D5, D6, D7, D9, D12, D14, D17, E2, E3, E4, E5, E8, E10, E13, E15, E19, F3, F4, F5, F11,
F18, G3, G8, G15, G17, H2, H7, H19, J1, J4, J18, K3, K17, L2, L6, L19, M1, M4, M16,
M18, N3, N17, P2, R1, R5, R7, R16, T3, T6, T10, T13, T19, U4, U7, U11, U14, U18, V2,
V5, V7, V12, V15, V17, W4, W7, W11, W14
– V_1V8 Power P
out
1.8 V 2 N1
– V_3V3 Power P
out
3.3 V 2 P1
– V_3V3_SD Power P
out
3.3 V 3 F6
– V_5V_IN Power P
in
5 V A2, A3, A4, B3, B4, C3, C4
H10 V_ECSPI Power P
in
1.8 / 3.3 V A15
W22 V_ENET Power P
in
1.8 / 2.5 / 3.3 V W12
– V_LICELL Power P
in
3 V D15
J12 V_UART Power P
in
1.8 / 3.3 V B15
A16 CSI_CLK_N MIPI_CSI I 1.8 V L17
B16 CSI_CLK_P MIPI_CSI I 1.8 V M17
A14 CSI_D0_N MIPI_CSI I 1.8 V J19
B14 CSI_D0_P MIPI_CSI I 1.8 V K19
A15 CSI_D1_N MIPI_CSI I 1.8 V K18
B15 CSI_D1_P MIPI_CSI I 1.8 V L18
A17 CSI_D2_N MIPI_CSI I 1.8 V M19
B17 CSI_D2_P MIPI_CSI I 1.8 V N19
A18 CSI_D3_N MIPI_CSI I 1.8 V N18
B18 CSI_D3_P MIPI_CSI I 1.8 V P18
A11 DSI_CLK_N MIPI_DSI O 1.8 V F19
B11 DSI_CLK_P MIPI_DSI O 1.8 V G19
A9 DSI_D0_N MIPI_DSI O 1.8 V D18
B9 DSI_D0_P MIPI_DSI O 1.8 V E18
A10 DSI_D1_N MIPI_DSI O 1.8 V E17
B10 DSI_D1_P MIPI_DSI O 1.8 V F17
A12 DSI_D2_N MIPI_DSI O 1.8 V G18
B12 DSI_D2_P MIPI_DSI O 1.8 V H18
A13 DSI_D3_N MIPI_DSI O 1.8 V H17
B13 DSI_D3_P MIPI_DSI O 1.8 V J17
A21 PCIE_REF_CLKN PCIe I/O 0.7 V T17
B21 PCIE_REF_CLKP PCIe I/O 0.7 V U17
A19 PCIE_RXN PCIe I 0.7 V R18
B19 PCIE_RXP PCIe I 0.7 V T18
A20 PCIE_TXN PCIe O 0.7 V P19
B20 PCIE_TXP PCIe O 0.7 V R19
2: Maximum load of 500 mA.
3: Maximum load of 400 mA.