User's Manual l MBa8Xx UM 0100 l © 2020, TQ-Systems GmbH
Page 24
3.8.4
Ethernet
The i.MX 8X CPU and thus the TQMa8Xx provides two independent RGMII interfaces. On the MBa8Xx, both interfaces are
configured as Gigabit Ethernet ports. The PHYs support IEEE 802.3 10BASE-Te, 100BASE-TX, and 1000BASE-T.
The I/O voltage of the RGMII signals is 1.8 V. Both PHYs are connected with their own PHY reset and interrupt signals.
TQMa8Xx
RJ45
(X19)
ENET0
RGMII0
ENET1
RGMII1
PHY #1
DP83867
PHY #2
DP83867
RJ45
(X18)
SMI
25 MHz
25 MHz
Figure 12: Block diagram Ethernet
Both transceivers are each connected with their own reset and interrupt signals, for which four GPIO signals of the TQMa8Xx are
used. The following table shows the signals used.
Table 25:
Reset and interrupt signals
Ethernet port Transceiver function MBa8Xx signal TQMa8Xx signal TQMa8Xx pin
Remark
Ethernet 1
Interrupt input
(Pin: INT)
ENET0_INT#
GPIO3_IO00
X2-91
Low-active / pulled-up to V_1V8
Reset output
(Pin: RESET#)
ENET0_RESET#
GPIO3_IO02
X2-92
Low-active / pulled-up to V_1V8
Ethernet 2
Interrupt input
(Pin: INT)
ENET1_INT#
GPIO3_IO01
X2-93
Low-active / pulled-up to V_1V8
Reset output
(Pin: RESET#)
ENET1_RESET#
GPIO3_IO03
X2-94
Low-active / pulled-up to V_1V8
