User's Manual l MBa57xx UM 0100 l © 2020, TQ-Systems GmbH
Page 39
4.2.16
100 mil headers
All signals not used on the TQMa57xx are routed to headers X12, X13, X36, X37, X44 ~ X51, and X56 on the MBa57xx.
Furthermore, some of the signals used are also routed to headers for reference and measurement purposes.
All headers have a 100 mil pitch.
The headers are positioned in such a way that adapter boards with customer-specific circuitry can easily be plugged in.
Illustration 23:
Block diagram headers X12, X13, X36, X37, X44 ~ X51, X56
The double grouping of the tables corresponds to the mechanical header arrangement on the MBa57xx.
Table 46:
Pinout 10/100 Mbit Ethernet ports, header X13, X12
Group
Signal
Pin
Signal
Group
Power
VCC3V3
1
X1
3
2
PR2_MII0_RXD[0]
ETH2_MII0
ETH2_MDIO
PR2_MDIO_DATA
3
4
PR2_MII0_RXD[1]
ETH2_MII0
ETH2_MDIO
PR2_MDIO_MDCLK
5
6
PR2_MII0_RXD[2]
ETH2_MII0
ETH2_MII0
PR2_MII0_COL
7
8
PR2_MII0_RXD[3]
ETH2_MII0
ETH2_MII0
PR2_MII0_CRS
9
10
PR2_MII0_MT_CLK
ETH2_MII0
ETH2_MII0
PR2_MII0_MR_CLK
11
12
PR2_MII0_TXD[0]
ETH2_MII0
ETH2_MII0
PR2_MII0_RXDV
13
14
PR2_MII0_TXD[1]
ETH2_MII0
ETH2_MII0
PR2_MII0_RXER
15
16
PR2_MII0_TXD[2]
ETH2_MII0
ETH2_MII0
PR2_MII0_RXLINK
17
18
PR2_MII0_TXD[3]
ETH2_MII0
Power
DGND
19
20
PR2_MII0_TXEN
ETH2_MII0
Group
Signal
Pin
Signal
Group
Power
VCC3V3
1
X1
2
2
PR2_MII1_RXD[0]
ETH2_MII0
ETH2_MDIO
PR2_MDIO_DATA
3
4
PR2_MII1_RXD[1]
ETH2_MII0
ETH2_MDIO
PR2_MDIO_MDCLK
5
6
PR2_MII1_RXD[2]
ETH2_MII0
ETH2_MII1
PR2_MII1_COL
7
8
PR2_MII1_RXD[3]
ETH2_MII0
ETH2_MII1
PR2_MII1_CRS
9
10
PR2_MII1_MT_CLK
ETH2_MII0
ETH2_MII1
PR2_MII1_MR_CLK
11
12
PR2_MII1_TXD[0]
ETH2_MII0
ETH2_MII1
PR2_MII1_RXDV
13
14
PR2_MII1_TXD[1]
ETH2_MII0
ETH2_MII1
PR2_MII1_RXER
15
16
PR2_MII1_TXD[2]
ETH2_MII0
ETH2_MII1
PR2_MII1_RXLINK
17
18
PR2_MII1_TXD[3]
ETH2_MII0
Power
DGND
19
20
PR2_MII1_TXEN
ETH2_MII0
