User's Manual l MBa57xx UM 0100 l © 2020, TQ-Systems GmbH
Page 12
4.1.2
I
2
C address mapping
Illustration 3:
Block diagram I
2
C buses on TQMa57xx and MBa57xx
The TQMa57xx offers two I
2
C interfaces, which are available on the TQMa57xx connectors as primary function.
I2C1 is a TQMa57xx internal I
2
C bus, which is exclusively used for the I
2
C devices on the TQMa57xx. This bus is not available.
The corresponding addresses can be taken from the User's Manual of the TQMa57xx (12).
I2C5 is routed to header X48 on the MBa57xx, no I
2
C devices are connected.
Further I
2
C interfaces can be provided by an adapted pin multiplexing.
The following table shows the signals used on the two I
2
C interfaces:
Table 8:
I
2
C signals
Signal
Direction
MBa57xx
Remark
I2C4_SDA
I/O
X1-88
2.7 kΩ PU to 3.3 V on MBa57xx
I2C4_SCL
O
X1-90
2.7 kΩ PU to 3.3 V on MBa57xx
I2C5_SDA
I/O
X1-94
2.7 kΩ PU to 3.3 V on MBa57xx
I2C5_SCL
O
X1-96
2.7 kΩ PU to 3.3 V on MBa57xx
The following table shows the I2C4 addresses used on the MBa57xx.
Table 9:
I2C4 address assignment
Reference
Device
Usage
7-bit address
D22
PCA9555PW
GPIO expander
0x20 / 010 0000b
D23
PCA9555PW
GPIO expander
0x21 / 010 0001b
D18
USB4604
USB Hub
0x2D / 010 1101b
D9
STMPE811Q
Touch Controller
0x41 / 100 0001b
N9
TLV320AIC3204
Audio Codec
0x18 / 001 1000b
D35
9FGV0441AKILFT
PCIe Clock
0x34 / 011 0100b
D21
TUSB8041
USB3.0 Hub
0x44 / 100 0100b
X41
PCIe
Lane 0
–
X29
mPCIe
Lane 1
–
X56
Header
RGB
–
