User's Manual l TQMa8XxS UM 0101 l © 2022, TQ-Systems GmbH
Page 29
3.7
CPLD
A CPLD is used to implement the boot configuration so that specification changes can be addressed flexibly. Instead of a
redesign of the digital logic, only a software change (CPLD configuration) is then necessary.
SLG46120V
(SLG4R42831V)
i.MX 8X
SMARC-Pins
GPIO (3x)
BOOT_MODE[3:0]
BOOT_SEL[2:0]
FORCE_RECOV#
GPIO
VDD
V_1V8_ANA
V_1V8_ANA
GPIO (4x)
3
4
GPI / VPP
VPP
Testpoint
Figure 27:
Block diagram CPLD
The input signals BOOT_SEL[2:0] and FORCE_RECOV# as well as the output signals BOOT_MODE[3:0] are connected to
programmable IO pins of the CPLD. Since due to the PMIC sequencing the CPU reset signal is strongly delayed (>100 ms), it is
ensured that valid output signals are present at the CPLD until the BOOT_MODE pins are sampled by the CPU. The SLG46120V
has a startup time of only 310 µs.
The CPLD is obtained and assembled already pre-programmed. Programming in the board after manufacturing or during
functional test is not necessary. However, test points are provided on the programming pins for development purposes. The
signals are assigned so that only external signals (SMARC pins) are applied to the programming pins. The customer-specific
programming gives the chip the designation SLG4R42831V.
