User's Manual l TQMa8XxS UM 0101 l © 2022, TQ-Systems GmbH
Page 21
3.3.3
LVDS / DSI / Display-Port
In addition to LVDS, the SMARC standard also specifies HDMI or DisplayPort. The Display Port signals are provided by MIPI_DSI0
via DSI-to-DP bridge. If DisplayPort is not used, both MIPI-DSI interfaces of the CPU can be connected to the SMARC LVDS/DSI
pins.
The MIPI_DSI0 data and clock signals are connected to the SMARC pins with 0-Ω bridges. When equipping the DisplayPort bridge
to use the DisplayPort, these 0-Ω bridges are not assembled. Thus, these DSI0 signals are then no longer available at the SMARC
pins.
The MIPI_DSI0_I2C0 interface of the CPU is used to provide the I2C_LCD signals. The enable signals for VDD and backlight are
multiplexed as GPIO signals to the SPI2 pins of the CPU. The backlight PWM signals are multiplexed to the GPIO0_00 pins of the
DSI interfaces.
i.MX 8X
MIPI_DSI0_DATA[3:0]
SMARC-Pins
DSI-2-DP
D[3:0]
I2C
L[1:0]
AUX
HPD
LVDS0/DSI0_D[3:0]
DP0_AUX
0R
DP0_LANE[1:0]
DP0_HPD
MIPI_DSI0_CLK
MIPI_DSI1_DATA[3:0]
MIPI_DSI1_CLK
LVDS0/DSI0_CLK
LCD[1:0]_BLKT_EN
LCD[1:0]_VDD_EN
LCD[1:0]_BLKT_PWM
LVDS1/DSI1_D[3:0]
LVDS1/DSI1_CLK
SPI2_x
MIPI_DSI[1:0]_
GPIO0_00
0R
DAC
I2C_LCD
MIPI_DSI0_I2C0
Figure 14: Block diagram LVDS / DSI / Display-Port
Due to the use of DisplayPort 1.1a, only two of the four data lanes provided in the SMARC standard (DP0_LANE0 & DP0_LANE1)
are used. Lane 2 and 3 remain unconnected.
The LVDS and DSI signals are also routed out on SMARC pins, but can only be used if DisplayPort is not used.
3.3.4
Camera Serial Interface (CSI)
The CSI of the i.MX 8X is directly connected to the SMARC connector, including the I
2
C bus provided for this purpose.
Since only two lanes are available at port CSI0, CSI1 is used instead. At CSI1 all four data lanes of the CPU are made available.
i.MX 8X
SMARC pins
MIPI_CSI0_I2C0
CAM_MCK
CSI1_RX[3:0]
I2C_CAM1
MIPI_CSI0_DATA[3:0]
CSI1_CK
MIPI_CSI0_CLK
MIPI_CSI0_MCLK_OUT
Figure 15: Block diagram CSI
The parallel CSI interface of the i.MX 8X is optionally provided at the CSI0 pins (not SMARC-compliant).
