Preliminary User's Manual l TQMa8Xx UM 0002 l © 2018, TQ-Systems GmbH
Page 11
3.2.2
Memory
3.2.2.1
DDR3L SDRAM
Depending on the ECC option, the TQMa8Xx can be equipped with two or three DDR3L memory chips with an effective memory
width of 32 bits. The third DDR3L memory chip for the ECC option uses 8 bits.
The interface timing complies with JEDEC standard DDR3-1866 with a maximum clock rate of 933 MHz.
Illustration 3:
Block diagram DDR3L interface
3.2.2.2
eMMC NAND flash
An eMMC is available on the TQMa8Xx as non-volatile memory for programs and data (e.g. bootloader, operating system,
application).
The following illustration shows the interface of the eMMC to the i.MX 8X:
Illustration 4:
Block diagram eMMC interface
The i.MX 8X supports MMC card transmission modes up to the current eMMC standard v5.1 or SD card standard 3.0.
The I/O voltage is 1.8 V to support the maximum clock rate of 200 MHz. This allows a data rate of up to 400 Mbyte/s in DDR mode
(HS400). The eMMC can be used as boot medium. The boot configuration is described in 3.2.1.3.
