User's Manual l MBa8x UM 0100 l © 2021, TQ-Systems GmbH
Page 39
I/O
Level
Group
Signal
Pin
Signal
Group
Level
I/O
O
VAR
SYSTEM
RESET_OUT#
29
30
GND
Power
0 V
P
I/O
1.8 V
FTM
FTM_CH0
31
32
USB_HSIC_STROBE
HSIC
1.8 V
I/O
I/O
1.8 V
FTM
FTM_CH1
33
34
USB_HSIC_DATA
HSIC
1.8 V
I/O
I/O
1.8 V
FTM
FTM_CH2
35
36
GND
Power
0 V
P
I/O
1.8 V
GPIO
GPIO2_IO17
37
38
CAN2_RX
CAN2
1.8 V
I
I/O
1.8 V
GPIO
GPIO2_IO21
39
40
CAN2_TX
CAN2
1.8 V
O
Table 30:
Pinout Header X64
I/O
Level
Group
Signal
Pin
Signal
Group
Level
I/O
P
12 V
Power
V_12V
1
2
V_3V3_MB
Power
3.3 V
P
P
5 V
Power
V_5V
3
4
V_1V8
Power
1.8 V
P
P
0 V
Power
GND
5
6
GND
Power
0 V
P
P
0 V
Power
GND
7
8
GND
Power
0 V
P
O
1.8 V
SYSTEM
PMIC2_FSOB
9
10
SPI0_CS1
SPI0
1.8 V
O
O
1.8 V
SYSTEM
PMIC1_FSOB
11
12
TEMP_EVENT#
SYSTEM
VAR
O
P
0 V
Power
GND
13
14
SPI1_CS0
SPI1
1.8 V
O
I/O
VAR
ADC
ADC_IN1
15
16
SPI1_CS1
SPI1
1.8 V
O
I/O
VAR
ADC
ADC_IN2
17
18
SPI1_SDI
SPI1
1.8 V
I
P
0 V
Power
GND
19
20
SPI1_SDO
SPI1
1.8 V
O
I/O
1.8 V
GPIO
GPIO1_IO14
21
22
SPI1_SCK
SPI1
1.8 V
O
I/O
1.8 V
GPIO
GPIO1_IO15
23
24
GND
Power
0 V
P
P
0 V
Power
GND
25
26
SPI2_CS0
SPI2
1.8 V
O
I
1.8 V
SAI1
SAI1_RXFS
27
28
SPI2_CS1
SPI2
1.8 V
O
I
1.8 V
SAI1
SAI1_RXC
29
30
SPI2_SDI
SPI2
1.8 V
I
P
0 V
Power
GND
31
32
SPI2_SDO
SPI2
1.8 V
O
O
1.8 V
SPDIF
SPDIF_EXT_CLK
33
34
SPI2_SCK
SPI2
1.8 V
O
P
0 V
Power
GND
35
36
GND
Power
0 V
P
I/O
1.8 V
I2C2
I2C2_SDA
37
38
SPDIF_RX
SPDIF
1.8 V
I
O
1.8 V
I2C2
I2C2_SCL
39
40
SPDIF_TX
SPDIF
1.8 V
O
3.14.21
JTAG
The JTAG interface is routed to a 20-pin header (X22). The required pull-ups of the lines TDI, TMS, TRST# and SRST# are available
on the MBa8x. All signal lines use 1.8 V as reference voltage.
TQMa8x
20 pol.
pin header
(X22)
JTAG _TCK
JTAG _TDI
JTAG _TDO
JTAG _TMS
JTAG_TRST#
Figure 26: Block diagram JTAG
The supply voltage at the connector can be set to V_1V8 or V_3V3_MB by means of an assembly option.
The JTAG interface is not ESD protected.
