Toshiba TMPM3V4, Manual

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25.6.4 Synchronous Serial Interface (SSP)
25.6.4.1 AC Measurement Condition
The letter "T" used in the equations in the table represents the period of the input clock (f
PCLK
) into
the internal prescaler.
・
Output levels : High = 0.7 × DVDD5, Low = 0.3 × DVDD5
・
Input levels: High = 0.9 × DVDD5, Low = 0.1 × DVDD5
・
Load capacitance: CL=30pF
・
Ta = −40 to 85°C
Note: The "Equation" column in the table shows the specifications under the conditions DVDD5 = 3.9V to
5.5V.
Parameter Symbol
Equation
fsys=40MHz
(m=4,n=12)
Unit
Min Max
SPCLK cycle (master)
T
m
(m)T
At least 100ns
or more
−
100
(10MHz)
ns
SPCLK cycle (slave)
T
s
(n)T −
300
(3.3MHz)
SPCLK rise up time
t
r
− 15 15
SPCLK fall down time
t
f
− 15 15
Master mode: SPCLK low-level pulse width t
WLM
(m)T/2 - 20.0 − 30
Master mode: SPCLK hig h -level pulse width
t
WHM
(m)T/2 - 20.0 − 30
Slave mode: SPCLK low-level pulse width
t
WLS
(n)T/2 - 10.0 − 140
Slave mode: SPCLK high- l evel pulse width
t
WHS
(n)T/2 - 10.0 − 140
Master mode:
SPCLK rise/fall to output data valid
t
ODSM
− 15 15
Master mode:
SPCLK rise/fall to output data hold
t
ODHM
(m)T/2 - 15 − 35
Master mode:
SPCLK rise/fall to input data valid delay time
t
IDSM
35 − 35
Master mode:
SPCLK rise/fall to input data hold
t
IDHM
5 − 5
Master mode:
SPFSS valid to SPCLK rise/fall
t
OFSM
(m)T - 15 (m)T + 15 85 to 115
Slave mode:
SPCLK rise/fall to output data valid delay time
t
ODSS
− (3T) + 35 110
Slave mode:
SPCLK rise/fall (Output data hold)
t
ODHS
(n)T/2 + (2T) − 200
Slave mode:
SPCLK rise/fall to input data valid delay time
t
IDSS
10 − 10
Slave mode:
SPCLK rise/fall to input data hold
t
IDHS
(3T) + 15 − 90
Slave mode:
SPFSS valid to SPCLK rise/fall
t
OFSS
(n)T - 20 − 280
TMPM3V6/M3V4
Page 507
2019-02-06