TOPWAY
LCD Module User Manual
LMT056DIDFWD-ABN
Document Name: LMT056DIDFWD-ABN-Manual-Rev0.2
Page: 6 of 14
6. AC Characteristics
6.1
TFT Controller Timing Characteristics
8080 Mode Write Timing
8080 Mode Read Timing
V
SS
=0V, V
DD
=5.0V, T
OP
=25
C
Item
Symbol
MIN.
TYP.
MAX.
Unit
System Clock Period(*1)
t
MCLK
1/f
MCLK
-
-
ns
Control Pulse High Width
Write
t
PWCSL
29
1.5*t
MCLK
-
ns
Read
51
1.3*t
MCLK
-
ns
Control Pulse Low Width
Write (next write cycle)
t
PWCSH
29
1.5*t
MCLK
-
ns
Write (next read cycle)
113
9*t
MCLK
-
ns
Read
113
9*t
MCLK
-
ns
Address Setup Time
t
AS
7.8
-
-
ns
Address Hold Time
t
AH
9
-
-
ns
Write Data Setup Time
t
DSW
11.5
-
-
ns
Write Data Hold Time
t
DHW
7.8
-
-
ns
Write Low Time
t
PWLW
28
-
-
ns
Read Data Hold Time
t
DHR
9.1
-
-
ns
Access Time
t
ACC
63.3
-
-
ns
Read Low Time
t
PWLR
58
-
-
ns
Rise Time
t
R
-
-
0.4
ns
Fall Time
t
F
-
-
0.4
ns
Chip select setup time
t
CS
9
-
-
ns
Chip select hold time to read signal
t
CSH
9
-
-
ns
Note:
*1. t
MCLK
is the System Clock Period, which may config by internal PLL setting
*2. LMT056DIDFWD is driving by external 10MHz, and clock up by enabling the SSD1963 internal PLL
*3. Suggested PLL clock setting is 200MHz
ZZZWRSZD\GLVSOD\VHX
LQIR#WRSZD\GLVSOD\VHX
