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Programmable Hardware Manual (PHM)
© Tibbo Technology Inc.
"W1 output" (on TX) and "W1 input" (on RX) cannot be remapped, while "W0 output"
(on RTS) can be reassigned to any suitable GPIO line. "W0 & W1 input" (on CTS)
can be remapped, but possible choices are limited to interrupt lines I0-7 (GPIO16-
23).
Clock/data mode
The clock/data interface is also a very popular reader interface. The ser. object
allows you to receive and send data streams in the clock/data format.
As the name implies, this interface requires two data lines - CLOCK and DATA. Here
is how these lines map to the "traditional" lines of the serial port:
TX
DATA output
RX
DATA input
RTS
CLOCK output
CTS
CLOCK input
As in the UART mode, "DATA output" (on TX) and "DATA input" (on RX) cannot be
remapped, while "CLOCK output" (on RTS) can be reassigned to any suitable GPIO
line. "CLOCK input" (on CTS) can be remapped, but possible choices are limited to
interrupt lines I0-7 (GPIO16-23).
No additional circuitry is required to handle clock/data streams.
For more information see the documentation for the serial (ser.) object found inside
the TIDE, TiOS, Tibbo BASIC, and Tibbo C Manual.
Wiegand and Clock/Data Circuit Examples
In the Wiegand mode, the W0&1in input of the serial port must receive a logical AND
of W0 and W1 output of attached Wiegand device. A simple AND gate will do the job
(figure A below). NOR-AND gates are more popular that AND gates, and these can
be used too (figure B). In case you are building a product that will also accept
clock/data input, you may need to control whether the W0&1in input should receive
a logical AND of the two lines, or just one of the lines. Schematic diagram C uses an
additional I/O line of the device to control this. When the control line is HIGH the
W0&1in input receives a logical AND of both W0 and W1 lines, when the control line
is LOW, the W0&1in input receives just the signal from the W0 line. Four gates are
required for this, so you will get away with using a single 74HC00 IC.
