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Thundercomm

TurboX D845 System on Module

Copyright © 2018 All Rights Reserved , Thundercomm Technology Co., Ltd.

25

UART, SPI, or I2C operation.
I2C is a two-wire bus that can be routed to multiple devices; each line of each bus need to supplement by a
2.2kΩ pull-up resistor

QUP Interface

PIN Name

Location

PIN

Voltage

Type

Description

Notes

BLSP_SPI0_MISO

CON2402

83

PX3

IO

QUP0 can be configured
to GPIO or UART or SPI or
I2C

BLSP_SPI0_MOSI

CON2402

81

PX3

IO

BLSP_SPI0_CLK

CON2402

85

PX3

IO

BLSP_SPI0_CS_L

CON2402

79

PX3

IO

BLSP_SPI2_MISO

CON2402

55

PX3

IO

QUP2 can be configured
to GPIO or UART or SPI or
I2C

BLSP_SPI2_MOSI

CON2402

57

PX3

IO

BLSP_SPI2_CLK

CON2402

51

PX3

IO

BLSP_SPI2_CS_L

CON2402

53

PX3

IO

BLSP_SPI11_MISO

CON2402

98

PX3

IO

QUP11 can be configured
to GPIO or UART or SPI or
I2C

BLSP_SPI11_MOSI

CON2402

96

PX3

IO

BLSP_SPI11_CLK

CON2402

100

PX3

IO

BLSP_SPI11_CS_L

CON2402

102

PX3

IO

BLSP_I2C4_SDA

CON2402

3

PX3

IO

QUP4 can be configured
to GPIO or UART or SPI or
I2C

BLSP_I2C4_SCL

CON2402

5

PX3

IO

SDC4_CMD

CON2401

91

PX3

IO

SDC4_DATA3

CON2401

89

PX3

IO

SDC4_CLK

CON2401

85

PX3

IO

QUP7 can be configured
to GPIO or UART or SPI or
I2C

SDC4_DATA2

CON2401

87

PX3

IO

SDC4_DATA1

CON2401

83

PX3

IO

SDC4_DATA0

CON2401

81

PX3

IO

APPS_I2C10_SDA

CON2402

78

PX3

IO

QUP10 can be configured
to GPIO or I2C

APPS_I2C10_SCL

CON2402

76

PX3

IO

TP_I2C_SDA

CON2402

45

PX3

IO

QUP5 can be configured
to GPIO or I2C

TP_I2C_SCL

CON2402

43

PX3

IO

Table 3.2- 10 QUP interface definition

3.2.11 Power on Interface

Dedicated PMIC circuits continuously monitor events that might trigger a power-on sequence. If an event
occurs, these circuits power on the IC, determine the device’s available power sources, enable the correct
source. It is longer than 1s with pressing power-on key, for power on event. And it is suggested for 3s
powering on system. Power on/off key signal can be connected to ground through CON2402.6; the other
power on method is: when using CBL_PWR_N pin connect to ground, insert battery or power supply

，

SOM

Summary of Contents for TurboX D845

Page 1: ...input output interfaces This SOM provides a variety of GPIO I2C UART and SPI standard interfaces In addition it supports two MIPI DSI four MIPI CSI and SOM common standard protocol interfaces such as USB3 1 PCIE2 1 3 0 I2S and SLIMBUS TurboX D845 SOM provides convenient and stable system solution for IOT field it can be embedded into the device on VR AR Drone Robot Smart Camera AI devices and any ...

Page 2: ... 2 and DisplayPort 1 4 data concurrency over USB Maximum concurrency configurations 3840x2400 at 60Hz primary 3840 x 2160 or 4096 x 2160 at 60Hz DP 2 x 2560 x 1600 at 60 fps primary 3840 x 2160 or 4096 x 2160 at 60fps DP Camera support Support 3 x 4 lane MIPI_CSI 1 x 2 lane MIPI_CSI Dual 14 bit ISP one Lite ISP Real time sensor input resolution 16 16 2 MP 32 MP 30 fps ZSL with a dual ISP 16 MP 30 ...

Page 3: ...ative DSD WCD9341 only MBHC and ANC 130 dB dynamic range 32 bit DAC Low power audio Low power low complexity 7 1 surround sound Voice codec support QCELP EVS EVRC EVRC B EVRC WB G 7 Gen G 729A AB GSM FR GSM EFR and GSM HR AMR NB and AMR WB Enhanced audio Surround sound advanced multichannel FluenceTM Pro noise cancellation enhanced speaker protection Qualcomm enhance 3D audio solution Qualcomm ste...

Page 4: ...highly multiplexed high speed baseline WCD9340 WCD9341 MI2S Full duplex stereo or up to quad channel Tx Rx MI2S x3 Up to eight channels for multi channel Tx Rx audio applications x1 GPIO 12 GPIO ports Others ADC Interface Support ADC interfaces used for input voltage sense battery temperature detection and general purpose ADC Touchscreen support Capacitive panels via ext IC I2C and interrupts Phys...

Page 5: ...ons TurboX D845 SOM is ideal for many applications including but not limited to AI Robotics Virtual Reality VR Augmented Reality AR Drones and Medical Devices Revision History Version Date Description V1 0 July 31 2018 Revised Release V1 1 Sep 28 2018 Update the pin definition description V1 2 Oct 8 2018 Update format ...

Page 6: ...Processing Subsystem 12 2 3 Secure Processing Unit SPU 13 2 4 ISP ISP280 14 2 5 Connection 14 3 Interfaces Description 15 3 1 Interfaces Parameter Definitions 15 3 2 Interfaces Detail Description 16 3 2 1 Power Supply Interface 16 3 2 2 Touchscreen Interface 17 3 2 3 Display Interface 17 3 2 4 Camera Interfaces 18 3 2 5 Audio Interface 20 3 2 6 USB DisplayPort Interface 21 3 2 7 PCIe Interface 22 ...

Page 7: ...erface 28 3 2 19 Antenna Interface 29 4 Connector PIN Summary 30 4 1 CON2401 BTB Connector 30 4 2 CON2402 BTB Connector 33 4 3 J2 BTB Connector 36 5 Electrical Characteristics 37 5 1 Absolute Maximum Ratings 37 5 2 Operating Conditions 37 5 3 Digital logic characteristics 38 5 3 1 Digital GPIO characteristics 38 5 3 2 SD card digital I O characteristics 39 5 4 MIPI 40 5 5 USB 40 5 6 PCIe 40 5 7 Di...

Page 8: ...Thundercomm TurboX D845 System on Module Copyright 2018 All Rights Reserved Thundercomm Technology Co Ltd 8 5 14 LED Current Driver 44 5 15 ADC 45 5 16 Power Consumption 46 5 17 Thermal 46 ...

Page 9: ...m on Module Copyright 2018 All Rights Reserved Thundercomm Technology Co Ltd 9 1 1 Major Components Location TurboX D845 SOM s major components as below map Figure 1 1 1 TurboX D845 SOM Key component Location 1 Physical Description ...

Page 10: ...dicates connectors detail information Part Reference Description Manufacturer Part Number Manufacturer CON2401 CON2402 BTB connectors used for connecting to Carrier Board FX10A 168P SV HIROSE J2 JTAG connector used for JTAG Debug AXG7160J7 Panasonic J3002 J5701 J5801 RF antenna connector J3002 is for 818000500 ECT Table 1 2 1 Connector part number and information ...

Page 11: ...rcomm TurboX D845 System on Module Copyright 2018 All Rights Reserved Thundercomm Technology Co Ltd 11 1 3 Package Drawing and Dimensions Figure 1 3 1 Top View Figure 1 3 2 Side View Figure 1 3 3 Bottom View ...

Page 12: ... New HAP DCVS v2 APIs for clock and bus voting dspCV_concurrency is deprecated Session restart SDK 3 x Camera streaming four tap points Dedicated bus for camera streaming on the cDSP Dedicated high speed bus for data transfer from the DDR to the cDSP FastCV software development kit with HVX acceleration 2 2 Visual Processing Subsystem Improved GPGPU Enhanced image processing for GPGPU use cases Na...

Page 13: ... 2 3 Secure Processing Unit SPU Qualcomm Trusted Execution Environment Isolates secure and non secure software operations Small code base rigorously reviewed Based on ARM s TrustZone architecture Secure Boot Deters unauthorized code execution Tamper resistant root of trust in ROM or e fuses Hardware Crypto FIPS certifiable cryptographic engines and HW keys for more robust and fast encrypt decrypt ...

Page 14: ...ment Bayer process and noise reduction for snapshot only Simple stats for special offline processing Muti pass outputs feeding to IPE 2 5 Connection 2 x 2 802 11ac with MU MIMO 160 MHz DBS support Bluetooth 5 0 Optional dedicated BT antenna support concurrent operation for WLAN and BT with and without dedicated BT antenna RF performance meets all carrier requirments Industry leading throughput Low...

Page 15: ...O 1 8 V only DO Digital output CMOS H High voltage tolerant nppdpukp Programmable pull resistor The default pull direction is indicated using capital letters and is a prefix to other programmable options NP pdpukp default no pull with programmable options following the colon PD nppukp default pull down with programmable options following the colon PU nppdkp default pull up with programmable option...

Page 16: ...Name Location PIN Type Description Notes VBATT CON2401 159 160 161 162 1 63 164 165 166 16 7 168 PI Power supply in for SOM all operations USB_VBUS CON2402 159 161 163 165 1 67 PO USB output during USB OTG operation VREG_LVS2A_1P8 CON2402 147 PO Low voltage switch supply output for sensor VREG_S4A_1P8 CON2402 123 125 127 PO SMPS power output for external CODEC Also can used for 1 8V IO pull up vol...

Page 17: ..._RST_N CON2402 49 PX3 DI TP reset signals Table 3 2 2 Touchscreen interfaces definition 3 2 3 Display Interface The SOM supports dual 4 lane MIPI_DSI interfaces 60fps Up to 3840 x 2400 Display PIN Name Location PIN Voltage Type Description Notes MIPI_DSI0_LANE3_N CON2402 13 DSI AO MIPI0 signals for MIPI LCM Compliant with MIPI Alliance Specification for Display Serial Interface MIPI_DSI0_LANE3_P C...

Page 18: ...ation PIN Voltage Type Description Notes CCI_I2C_SDA0 CON2401 143 PX3 OD CCI0 Date signal already pull up on SOM CCI_I2C_SCL0 CON2401 141 PX3 OD CCI0 Clock signal already pull up on SOM CAM0_PWDN CON2401 113 PX3 DO Camera power down signal CAM0_RSTN CON2401 99 PX3 DO Camera reset signal CAM0_STROBE CON2401 121 PX3 DI Camera STROBE signal CAM0_DVDD_EN CON2401 131 LV DO Camera DVDD LDO enable signal...

Page 19: ...CON2401 33 CSI AI MIPI Signals of Camera1 Compliant with MIPI Alliance Standard Specification MIPI_CSI1_LANE3_P CON2401 35 CSI AI MIPI_CSI1_LANE2_P CON2401 39 CSI AI MIPI_CSI1_LANE2_N CON2401 41 CSI AI MIPI_CSI1_LANE1_N CON2401 45 CSI AI MIPI_CSI1_LANE1_P CON2401 47 CSI AI MIPI_CSI1_LANE0_N CON2401 51 CSI AI MIPI_CSI1_LANE0_P CON2401 53 CSI AI MIPI_CSI1_CLK_N CON2401 57 CSI AI MIPI_CSI1_CLK_P CON2...

Page 20: ...nt with MIPI Alliance Standard Specification MIPI_CSI3_LANE1_P CON2401 76 CSI AI MIPI_CSI3_LANE0_P CON2401 80 CSI AI MIPI_CSI3_LANE0_N CON2401 82 CSI AI MIPI_CSI3_CLK_N CON2401 86 CSI AI MIPI_CSI3_CLK_P CON2401 88 CSI AI CAM_MCLK3 CON2401 104 PX3 DO Camera main clock output CAM3_PWDN CON2401 111 PX3 DO Camera power down signal CAM3_RSTN CON2401 125 PX3 DO Camera reset signal CAM3_DVDD_EN CON2401 1...

Page 21: ...2S1_DATA1 CON2402 86 PX3 IO MI2S1_DATA0 CON2402 88 PX3 IO MI2S2_WS CON2402 56 PX3 IO I2S2 signals Compliant with Philips I2S Bus Specifications MI2S2_SCK CON2402 58 PX3 IO MI2S2_DATA0 CON2402 60 PX3 IO MI2S2_DATA1 CON2402 62 PX3 IO MI2S3_WS CON2402 64 PX3 IO I2S3 signals Compliant with Philips I2S Bus Specifications MI2S3_DATA1 CON2402 66 PX3 IO MI2S3_DATA2 CON2402 68 PX3 IO MI2S3_DATA0 CON2402 70...

Page 22: ...DP AUX signal switch select indicate USB2_SS_RX_M CON2402 99 DI USB 3 0 Signals Compliant with USB 3 1 standard specification Require differential impedance of 90Ω USB2_SS_RX_P CON2402 101 DI USB2_SS_TX_P CON2402 105 DO USB2_SS_TX_M CON2402 107 DO USB2_HS_DP CON2402 106 IO USB 2 0 Signals Compliant with USB 2 0 standard specification USB2_HS_DM CON2402 108 IO Table 3 2 6 USB DP interface definitio...

Page 23: ...re SPI signals SSC_SPI1_MOSI CON2401 151 PX12 DO SSC_SPI1_CLK CON2401 153 PX12 DO SSC_MAG_CS_L CON2401 135 PX12 DO SSC_GYRO_CS_L CON2401 137 PX12 DO SSC_ACCEL_CS_L CON2401 139 PX12 DO SSC_SPI2_CS_L CON2401 142 PX12 DO Snapdragon Sensor Core SPI signals SSC_SPI2_MOSI CON2401 144 PX12 DO PCIE_0_CLK_REQ CON2401 6 PX3 DI PCIe clock require signal need to reserve pull up resistor PCIE_0_RST_N CON2401 2...

Page 24: ...pacitance less than 1 0pF Each trace needs to be next to a ground plane SDIO SDC2 Interface PIN Name Location PIN Voltage Type Description Notes SDC2_CLK CON2401 46 PX2 DO SD card signals SD_CARD_DET_N need pull up to PX3 SDC2_CMD CON2401 48 PX2 IO SDC2_DATA3 CON2401 56 PX2 IO SDC2_DATA2 CON2401 58 PX2 IO SDC2_DATA1 CON2401 54 PX2 IO SDC2_DATA0 CON2401 52 PX2 IO SD_CARD_DET_N CON2401 50 PX3 DI SDI...

Page 25: ...2C4_SDA CON2402 3 PX3 IO QUP4 can be configured to GPIO or UART or SPI or I2C BLSP_I2C4_SCL CON2402 5 PX3 IO SDC4_CMD CON2401 91 PX3 IO SDC4_DATA3 CON2401 89 PX3 IO SDC4_CLK CON2401 85 PX3 IO QUP7 can be configured to GPIO or UART or SPI or I2C SDC4_DATA2 CON2401 87 PX3 IO SDC4_DATA1 CON2401 83 PX3 IO SDC4_DATA0 CON2401 81 PX3 IO APPS_I2C10_SDA CON2402 78 PX3 IO QUP10 can be configured to GPIO or ...

Page 26: ...ble Stage 1 reset software configurable bark PMIC generates interrupt giving the MSM device the opportunity to fix the problem or gracefully reset the system Example events that can cause a bark Over temperature indicates system is getting too hot PMIC watchdog indicates that it has not kicked Stage 2 software configurable bite If reset is ignored PMIC will force a reset event selectable by softwa...

Page 27: ...02 10 PX3 DI Volume up key signal Low active Table 3 2 13 Keys interface definition 3 2 14 Sensor Interrupt Interface All these interfaces dedicate to below sensors Sensor Interrupt PINs PIN Name Location PIN Voltage Type Description Notes MAG_INT CON2401 134 PX3 DI Magnetometer sensor interrupt MAG_DRDY_INT CON2401 136 PX3 DI Magnetometer data ready interrupt GYRO_INT CON2401 138 PX3 DI Gyroscope...

Page 28: ...negative input signal BATT_THERM CON2402 144 BATT_THERM _BIAS 2 7V AI Battery temperature sense input signal Table 3 2 16 Battery interface definition 3 2 17ADCs Interface The ADC input signal use as analog multiplexer function ADCs PINs PIN Name Location PIN Voltage Type Description Notes ADC_IN_5V CON2402 152 MV AI ADC input can be configured as 1 8V or 5V ADC_IN_1P8V CON2402 154 LV AI ADC input...

Page 29: ...sitive port LPG_OUT_4 Table 3 2 18 PWMs and LED Current Driver interface definition 3 2 19Antenna Interface The SOM provides the fully integrated WLAN and Bluetooth function The WLAN and Bluetooth share the antenna port with 50ohm impedance WLAN supports 2 2 multiple input multiple output MIMO with two spatial streams IEEE802 11 a b g n ac WLAN standards Supports Bluetooth 5 0 HS enabling seamless...

Page 30: ...2 PCIE0_TX_P 13 GND 14 GND 15 MIPI_CSI0_LANE1_N 16 PCIE0_REFCLK_P 17 MIPI_CSI0_LANE1_P 18 PCIE0_REFCLK_M 19 GND 20 GND 21 MIPI_CSI0_LANE0_N 22 PCIE0_RX_P 23 MIPI_CSI0_LANE0_P 24 PCIE0_RX_M 25 GND 26 GND 27 MIPI_CSI0_CLK_P 28 UFS2_L0_RX_M 29 MIPI_CSI0_CLK_N 30 UFS2_L0_RX_P 31 GND 32 GND 33 MIPI_CSI1_LANE3_N 34 UFS2_L0_TX_P 35 MIPI_CSI1_LANE3_P 36 UFS2_L0_TX_M 37 GND 38 GND 39 MIPI_CSI1_LANE2_P 40 U...

Page 31: ...CSI2_LANE2_P 70 MIPI_CSI2_LANE0_P 71 MIPI_CSI2_LANE2_N 72 GND 73 GND 74 MIPI_CSI3_LANE1_N 75 MIPI_CSI2_LANE3_P 76 MIPI_CSI3_LANE1_P 77 MIPI_CSI2_LANE3_N 78 GND 79 GND 80 MIPI_CSI3_LANE0_P 81 SDC4_DATA0 82 MIPI_CSI3_LANE0_N 83 SDC4_DATA1 84 GND 85 SDC4_CLK 86 MIPI_CSI3_CLK_N 87 SDC4_DATA2 88 MIPI_CSI3_CLK_P 89 SDC4_DATA3 90 GND 91 SDC4_CMD 92 CAM_MCLK0 93 GND 94 GND 95 CAM1_RSTN 96 CAM_MCLK1 97 CAM...

Page 32: ...X_M 129 CAM1_DVDD_EN 130 PCIE1_TX_P 131 CAM0_DVDD_EN 132 GND 133 CBL_PWR_N 134 MAG_INT 135 SSC_MAG_CS_L 136 MAG_DRDY_INT 137 SSC_GYRO_CS_L 138 GYRO_INT 139 SSC_ACCEL_CS_L 140 ACCEL_INT 141 CCI_I2C_SCL0 142 SSC_SPI2_CS_L 143 CCI_I2C_SDA0 144 SSC_SPI2_MOSI 145 CCI_I2C_SDA1 146 SSC_SPI2_CLK 147 CCI_I2C_SCL1 148 SSC_SPI2_MISO 149 SSC_SPI1_MISO 150 VREG_LVS1A_1P8 151 SSC_SPI1_MOSI 152 VREG_L21A_2P95 15...

Page 33: ...1_LANE0_P 17 GND 18 GND 19 MIPI_DSI0_LANE2_N 20 MIPI_DSI_CLK_P 21 MIPI_DSI0_LANE2_P 22 MIPI_DSI_CLK_N 23 GND 24 GND 25 MIPI_DSI0_CLK_N 26 MIPI_DSI1_LANE2_P 27 MIPI_DSI0_CLK_P 28 MIPI_DSI1_LANE2_N 29 GND 30 GND 31 MIPI_DSI0_LANE1_N 32 MIPI_DSI1_LANE3_N 33 MIPI_DSI0_LANE1_P 34 MIPI_DSI1_LANE3_P 35 GND 36 GND 37 MIPI_DSI0_LANE0_N 38 MIPI_DSI1_LANE1_N 39 MIPI_DSI0_LANE0_P 40 MIPI_DSI1_LANE1_P 41 GND 4...

Page 34: ...PPS_I2C10_SCL 77 GPIO_49 78 APPS_I2C10_SDA 79 BLSP_SPI0_CS_L 80 MI2S1_WS 81 BLSP_SPI0_MOSI 82 MI2S1_MCLK 83 BLSP_SPI0_MISO 84 MI2S1_SCK 85 BLSP_SPI0_CLK 86 MI2S1_DATA1 87 CC_DIR 88 MI2S1_DATA0 89 CODEC_RST_N 90 CODEC_SPI_MISO 91 CODEC_SPI_CLK 92 CODEC_INT1_N 93 CODEC_SPI_MOSI 94 CODEC_INT2_N 95 CODEC_SPI_CS_N 96 BLSP_SPI11_MOSI 97 GND 98 BLSP_SPI11_MISO 99 USB2_SS_RX_M 100 BLSP_SPI11_CLK 101 USB2_...

Page 35: ..._AUX_P 131 GPIO_128 132 EDP_AUX_N 133 GPIO_135 134 VCOIN 135 GPIO_129 136 MSM_UART_RX 137 NC 138 MSM_UART_TX 139 VREG_BOB 140 USB_CC2 141 VREG_BOB 142 USB_CC1 143 PWM_OUTPUT2 144 BATT_THERM 145 PWM_OUTPUT1 146 HOME_KEY 147 VREG_LVS2A_1P8 148 PM845_GPIO10 149 VREG_L19A_3P0 150 PM845_GPIO13 151 R_LED 152 ADC_IN_5V 153 B_LED 154 ADC_IN_1P8V 155 G_LED 156 GND 157 GND 158 IBATT_SENSE_P 159 USB_VBUS 160...

Page 36: ...Co Ltd 36 4 3 J2 BTB Connector Pin Signal Name Pin Signal Name 1 MSM_JTAG_TMS 9 MSM_JTAG_SRST_N 2 MSM_JTAG_TCK 10 MSM_UART_TX 3 MSM_JTAG_TDO 11 MSM_UART_RX 4 MSM_JTAG_TDI 12 VREG_S4A_1P8 5 MSM_JTAG_TRST_N 13 MSM_PS_HOLD 6 PHONE_ON_N 14 FORCE_USB_BOOT 7 PM_RESIN_N 15 WDOG_DISABLE 8 GND 16 MSM_RESOUT_N ...

Page 37: ..._CONN_VSENSE_M RSENSE_EXT_M RSENSE_EXT_P 0 5 6 V ESD ESD HBM model rating 2k KV ESD CDM model rating 4k KV Table 5 1 1 Absolute rating condition Notes for the ESD it will be valid and available only when the module is fully tested and approved in the Initial Production stage 5 2 Operating Conditions The SOM needs to be desinged in the operatin conditons which is shown as below table Parameters Min...

Page 38: ...d storage min and max temperature is only when the module is fully tested and approved in the Initial Production stage 5 3 Digital logic characteristics The digital I O s performance depends on its pad type usage and power supply voltage The SOM IO voltage level is the same with VDDPX_3 except the SD card and analog input output The I2C USB MIPI and UART comply with the standards 5 3 1 Digital GPI...

Page 39: ...erformance 5 3 2 SD card digital I O characteristics The SD card is powered by P2 supply the power is 1 8V and 2 96V the following table shows the SD card digital I O characteristics Parameter Description Min Typical Max Units VIH High level input voltage 1 27 0 625 x VDDPX_2 2 VDDPX_2 0 3 V VIL Low level input voltage 0 3 0 3 0 58 0 25 x VDDPX_2 V VHYS Schmitt hysteresis voltage 100 mV RPULL UP P...

Page 40: ... for CSI 2 v1 3 RAW7 not supported DPCM predictor 2 not supported MIPI Alliance Specification for DPHY v1 2 None MIPI Alliance Specification for CPHY v1 0 The maximum supported data rate is 1 5Gsps Table 5 5 2 MIPI_CSI 5 5 USB The SOM supports USB standards and exceptions Applicable standard Feature exceptions Universal Serial Bus Specification Revision 3 1 August 11 2014 or later SS Gen 2 UTMI Sp...

Page 41: ... Low power Interchip Media Bus Version 1 01 01 None Table 5 9 1 SLIMbus 5 9 SDIO The SOM Supports SD standards and exceptions Applicable standard Feature exceptions Secure Digital Physical Layer Specification version 3 0 None SDIO Card Specification version 3 0 None Table 5 10 1 SDIO 5 10 I2S The SOM I2S standards and exceptions Legacy I2S interfaces for primary and secondary microphones and speak...

Page 42: ...tional pin can be used for a master clock supplied by the MSM device the master clock is often used in the external devices to drive their oversampling logic The LPASS clock controller can provide master clocks from independent clock dividers to the I2S bit clock dividers Applicable standard Feature exceptions Philips I2S Bus Specifications revised June 5 1996 None Table 5 11 1 I2S Figure 5 11 1 I...

Page 43: ...g internal SCK Frequency 24 576 MHz T Clock period 40 69 ns t HC Clock high 0 45 T 0 55 T ns t LC Clock low 0 45 T 0 55 T ns t sr SD and WS input setup time 8 14 ns t hr SD and WS input hold time 0 ns t dtr SD and WS output delay 6 10 ns Using external SCK Frequency 24 576 MHz T Clock period 40 69 ns t HC Clock high 0 45 T 0 55 T ns t LC Clock low 0 45 T 0 55 T ns t sr SD and WS input setup time 8...

Page 44: ...operly updating the state of charge when a battery is reconnected Using precise measurements of battery voltage current and temperature the fuel gauging algorithm compensates for the variation in battery characteristics across temperature changes and aging effects This provides a dependable state of charge estimate throughout the entire life of the battery and across a broad range of operating con...

Page 45: ... Typ Max Units Expected use 1 1 channel end to end accuracy Calibrated data result 11 6 11 mV 1 1 channel end to end accuracy with internal pull up Calibrated data result 12 5 7 12 5 mV 1 3 channel end to end accuracy Calibrated data result 20 10 20 mV ADC resolution LSB 114 441 μV ADC conversion time 1K decimation ratio 4 8MHz sample clock 515 μs Current consumption VADC active 450 500 μA Table 5...

Page 46: ...3 Normal Operation Current Sleep Mode No LCD No camera WIFI ON mA TBD WIFi OFF mA TBD 4 Leakage current uA TBD Table 5 17 1 Power Consumption 5 17 Thermal This chart records thermal test data to make sure the SOM working on highest performance strong suggest make solution for heat sink Table 4 18 1 describes SOM thermal test point Thermal Test Condition 1 Test case The test script of CPU HDMI Out ...

Page 47: ...s Reserved Thundercomm Technology Co Ltd 47 Thermal Test Result Test Location Temperature Max T 1 Environment Temperature 25 2 UFS 34 6 9 6 3 PM845 38 6 13 6 4 DDR 33 9 8 9 5 PMI8998 35 5 10 5 6 WIFI 33 8 8 8 7 PCB 29 7 4 7 Figure 5 18 1 Thermal Data Heat Sink Design ...

Page 48: ...generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation If this equipment does cause harmful interference to radio or television reception which can be determined by turning the equipment o...

Page 49: ...d by Federal Communications Commission to operate with the antenna types listed below with the maximum permissible gain indicated Antenna types not included in this list that have a gain greater than the maximum gain indicated for any type listed are strictly prohibited for use with this device Internal Identification Antenna Description Antenna type Maximum antenna gain Antenna Type 1 Bluetooth a...

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