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5.2.5
USB
The C865 DEV KIT implements one USB Supper speed interface on the Secondary High Speed
Expansion Connector.
The Supper Speed USB of HS2 and High Speed USB of HS1 can be combined to one USB3.0 port.
5.2.6
Other signals on Secondary High Speed Connector
The C865 Dev main IO board implements more GPIOs on the secondary high-speed expansion
connector. The GPIOs are 1.8 V voltage rail.
GPIO-CC: Connects to GPIO_82 of SM8250 SoC. Can be configured as PCIE1 Reset.
GPIO-DD: Connects to GPIO_83 of SM8250 SoC. Can be configured as PCIE1 Clock Request.
GPIO-EE: Connects to GPIO_84 of SM8250 SoC. Can be configured as PCIE1 Wake.
GPIO-FF: Connects to GPIO_85 of SM8250 SoC. Can be configured as PCIE2 Reset.
GPIO-GG: Connects to GPIO_86 of SM8250 SoC. Can be configured as PCIE2 Clock Request.
GPIO-HH: Connects to GPIO_87 of SM8250 SoC. Can be configured as PCIEI2 Wake.
GPIO-II: Connects to GPIO_78 of SM8250 SoC. Can be configured as Camera2 Reset.
GPIO-JJ: Connects to GPIO_47 of SM8250 SoC. Can be configured as Camera2 power down,
QUP 14 CS or BOOT CONFIG 2.
PMIC_SPMI_CLK: Can be connected to SDX55 module.
PMIC_SPMI_DATA: Can be connected to SDX55 module.
