Preliminary
THCV245A_Rev.0.90_E
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6.26 Interrupt monitoring
Interrupt (INT) detects occurrence of internal error or status signal and then, latch the detected state.
Interrupt factor can be cleared by particular register write “1” access.
Interrupt factor can be masked to “0” fixed by particular register appropriate write access.
Table 42.
Interrupt monitoring
As a register, interrupt detected state is “1” and cleared state is “0”. When multiple interrupt sources are
activated, the OR operated result is indicated as IC external INT pin output, which at the same time can be sent
to Sub-Link counterpart device.
As an external INT pin output, open drain output interrupt detected state is “Low” and cleared state is “Hi-Z”,
while INT pin CMOS push-pull output interrupt detected state is “High” and cleared state is “Low”.
Table 43.
INT pin output control
INT interrupt function is supposed to be cleared before start monitoring any desired status because INT status
may have been changed before monitoring activation.
Module
INT
CLEAR
MASK/EN/OFF
MIPI
R_ERR_CRC
R_CRC_ERR_CLR
R_CRC_CMP_MSK
MIPI
R_ERR_ECCCOR
R_ECC_CRCT_ERR_CLR
R_ECC1_CMP_MSK
MIPI
R_ERR_ECCDBL
R_ECC_DOUBLE_ERR_CLR
R_ECC2_CMP_MSK
MIPI
R_ERR_ID
R_ERR_ID_CLR
R_ERR_ID_MSK
MIPI
R_ERR_SOTSYNC[3:0]
R_SOT_SYNC_HS_CLR[3:0]
R_ERR_SOT_HS_MSK_R[3:0]
MIPI
R_ERR_SYNCCODE[3:0]
R_SOT_SYNCCODE_CLR[3:0]
R_RX_IGNORE_DERR[3:0]
MIPI
R_ERR_FRAMESYNC[3:0]
R_ERR_FR_SYNC_ON_CLR[3:0]
R_ERR_FR_SYNC_MSK_R[3:0]
MIPI
R_ERR_CONTROL[4:0]
R_ERR_CTL_CLR[4:0]
R_ERR_CTL_MSK[4:0]
MIPI
R_INT_FS[3:0]
R_INT_FS_ON_CLR[3:0]
R_INT_FS_MSK_R[3:0]
MIPI
R_INT_FE[3:0]
R_INT_FE_ON_CLR[3:0]
R_INT_FE_MSK_R[3:0]
Main-Link
R_DHNDL_INT
R_DHNDL_INT_CLR
R_DHNDL_INT_MSK
GPIO
R_GPIO_INT_DETECT[3:0]
R_GPIO_INTC_DETECT[3:0]
R_GPIO_INTM_DETECT[3:0]
Sub-Link
R_INT_EXTERNAL
R_INTC_EXTERNAL
R_INTM_EXTERNAL
Sub-Link
R_INT_CKSUM_ERR
R_INTC_CKSUM_ERR
R_INTM_CKSUM_ERR
Sub-Link
R_INT_I2C_TMOUT
R_INTC_I2C_TMOUT
R_INTM_I2C_TMOUT
Sub-Link
R_INT_SLINK_PROTERR
R_INTC_SLINK_PROTERR
R_INTM_SLINK_PROTERR
Sub-Link
R_INT_SLINK_TMOUT
R_INTC_SLINK_TMOUT
R_INTM_SLINK_TMOUT
Sub-Link
R_INT_LOCKN
R_INTC_LOCKN
R_INTM_LOCKN
Sub-Link
R_INT_HTPDN
R_INTC_HTPDN
R_INTM_HTPDN
Sub-Link
R_INT_SLAVESIDE
R_INTC_SLAVESIDE
R_INTM_SLAVESIDE
Sub-Link
R_INT_EXTI2C_ACSEND
R_INTC_EXTI2C_ACSEND
R_INTM_EXTI2C_ACSEND
Sub-Link
R_INT_EXTI2CS_BUSCLR
R_INTC_EXTI2CS_BUSCLR
R_INTM_EXTI2CS_BUSCLR
Sub-Link
R_INT_EXTI2CS_NACK
R_INTC_EXTI2CS_NACK
R_INTM_EXTI2CS_NACK
Sub-Link Slave 2-wire master bus clear end
Sub-Link Slave 2-wire NACK detection
Sub-Link protocol error
Sub-Link access time out error
Main-Link LOCKN transition
Main-Link HTPDN transition
Sub-Link Slave side factor
remote 2-wire access on Sub-Link end
MIPI SYNCCODE SoT 1bit error
MIPI FRAMESYNC FS/FE position error
MIPI Control state error
MIPI FS
MIPI FE
Main-Link Data Handle error
GPIO input transition detect
IC Internal event except Sub-Link
Internal register Checksum error
2-wire access time out error
MIPI SoT sequence not detected error
Description
MIPI CRC error
MIPI ECC 1bit error
MIPI ECC 2bit error
MIPI ID error
(MIPI ID is not equal to Main-Link setting)
Addr(h)
Bits
Register
w idth
R/W
Description
Default
0x1041
[0]
R_INT_CMOSEN
1
R/W
[IO] INT CMOS/OpenDrain Select
0:OpenDrain
1:CMOS
1'h0
