Themis RES-32DCX, Installation Manual

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C-13
Themis Computer
C—BIOS Setup Utility
Advanced Setup
C.4.5 X Advanced Chipset Control
Access the submenu to make changes to the following settings.
C.4.5.1 SERR Signal Condition
This setting specifies the ECC Error conditions that an SERR# is to be asserted. The
options are None,
Single Bit , Multiple Bit, and Both.
C.4.5.2 4GB PCI Hole Granularity
This feature allows you to select the granularity of PCI hole for PCI slots. If MTRRs
are not enough, this option may be used to reduce MTRR occupation. The options
are:
256 MB , 512 MB, 1GB and 2GB.
C.4.5.3 Memory Branch Mode
This option determines how the two memory branches operate. System address
space can either be interleaved between the two branches or Sequential from one
branch to another. Mirror mode allows data correction by maintaining two copies of
data in two branches. Single Channel 0 allows a single DIMM population during
system manufacturing. The options are
Interleave , Sequential, Mirroring, and Sin-
gle Channel 0.
C.4.5.4 Branch 0 Rank Sparing
Select enable to enable the sparing feature for Branch 0 of memory bus. The options
are Enabled and Disabled .
C.4.5.5 Branch 1 Rank Sparing
Select enable to enable the sparing feature for Branch 1 of memory bus. The options
are Enabled and Disabled .
Caution: Be careful when changing the Advanced settings. Incorrect values en-
tered may cause system malfunction. Also, a very high DRAM frequency or incor-
rect DRAM timing may cause system instability. When this occurs, revert to the
default setting.