Cinterion
®
MV31-W Hardware Interface Description
5.5 Timing Sequence Requirement
75
t
MV31-W_HID_v01.009a
2022-04-27
Public / Preliminary
Page 54 of 76
5.5
Timing Sequence Requirement
5.5.1
Power On Timing Requirement
•
Requirements:
- +3.3V power should be stable earlier than Full_Card_Power_Off
- Compliance with PCI Express
®
Card Electromechanical Specification
Figure below shows the M.2 adapter power-up sequence for an adapter from the system power
rail.
Figure 26:
Power-up timing sequence
Tsettle
is the time it takes all Power Rails to reach their minimum operating voltage (depending
on System power rails). Power Valid is when all voltage supply rails have reached their respec-
tive Vmin.
Table 22:
Power up timing information
Symbol
Parameter
Min
Max Units
T
PVPGL
Power Valid to PERST#
input inactive
Implementation spe-
cific: 50ms recom-
mended
ms
T
PERS#CLK
REFCLK stable before
PERST# inactive
100
µs
