Thales Cinterion LGA User Manual Download

Page: 29 / 36

Cinterion

LGA DevKit User Guide

9.1 LGA DevKit SM

lga_devkit_ug_v03

2020-05-29

Public / Released

Page 29 of 36

GND

T27A1132-80SSG0PBNA01RTC

2x4_HEAD_SMD

0R_np

2x4_HEAD_SMD

GND

47k

2x4_HEAD_SMD

100nF

GND

100nF

GND

100nF

GND

100nF

GND

100nF

GND

100nF

SSSS811101

GND

2x8_HEAD_SMD

2x6_HEAD_SMD

GND

470k

TLV6741_np

GND

74LVCH2T45GT

GND

74LVCH2T45GT

GND

74LVCH2T45GT

GND

74LVCH2T45GT

GND

BC847

47k

47k_np

100nF_np

100nF

4k7

100R

74LVCH2T45GT

GND

74LVCH2T45GT

GND

74LVCH2T45GT

GND

74LVCH2T45GT

GND

100nF

GND

100nF

2x6_HEAD_SMD

_np

GND

_np

33pF

GND

1uF

GND

847

10k

_np

BC847

GND

47k

CDBQR70

ASC0.1

ASC0.2

ASC1

DAI

LGA DevKit S+M

U$1

GND

ADC1_IN

ADC2_IN

GND

TXD2_GPIO10

SD_WP(GPIO8)

SPIDI

SD_DET(GPIO7)

SD_CMD(GPIO6)

SD_CLK(GPIO5)

I2CCLK

VUSB_IN

USC5

ISENSE

USC6

CCCLK

VSIM

CCIO

CCRST

CCIN

CCGND

USC4

USC3

USC2

USC1

USC0

BATTEMP

SYNC

RXD1

RXD0

TXD1

TXD0

VDDLP

VCHARGE

CHARGEGATE

GND

BATT+

VEXT

RING0

DSR0

RTS0

DTR0

RTS1

CTS0

CTS1

DCD0

EMERG_RST

IGT

AGND

MICN1

MICP1

MICP2

MICN2

EPN1

EPP1

EPP2

EPN2

VMIC

VSENSE

USB_DN

USB_DP

I2CDAT

SD_0(GPIO1)

SD_1(GPIO2)

SD_2(GPIO3)

SD_3(GPIO4)

SPICS

RXD2_GPIO9

TP_ENV

PWR_IND

DAC_OUT

GND

CON7

CON11

CON13

R24

CON10

CON9

C24

C25

C26

C27

C28

C29

C32

C33

CON12

CON14

TP7

TP8

TP9

TP13

TP14

TP15

TP19

TP20

TP21

TP22

TP23

TP24

TP25

TP26

TP27

TP28

TP29

TP30

TP31

TP32

TP33

R51

IC8

TP34

TP35

TP36

TP100

TP38

TP39

TP40

TP41

TP37

TP42

TP43

TP44

TP45

TP46

TP47

TP48

R15

IC14

DIR

VCC-A

VCC-B

GND

IC15

DIR

VCC-A

VCC-B

GND

IC2

DIR

VCC-A

VCC-B

GND

IC16

DIR

VCC-A

VCC-B

GND

IC5

DIR

VCC-A

VCC-B

GND

IC17

DIR

VCC-A

VCC-B

GND

IC6

DIR

VCC-A

VCC-B

GND

IC18

DIR

VCC-A

VCC-B

GND

TP1

TP2

TP3

TP49

TP50

TP51

T2A

T2B

R49

R50

R59

C58

C60

R61

R64

R65

R66

R67

R68

R69

R70

R71

R72

R73

IC3

DIR

VCC-A

VCC-B

GND

IC19

DIR

VCC-A

VCC-B

GND

IC21

DIR

VCC-A

VCC-B

GND

IC22

DIR

VCC-A

VCC-B

GND

C59

C61

C62

C63

C64

C65

C66

JP6

JP7

SCL

VSS

SDA

VCC

TP52

TP53

TP54

TP55

C67

C68

C69

C70

C71

R82

C72

R83

TP59

TP60

T3B

R89

TP11

TP12

TP16

TP17

TP18

TP73

TP74

TP82

TP83

RTS0_X100/[2]

CTS0_X100/[2]

DTR0_X100/[2]

DSR0_X100/[2]

DCD0_X100/[2]

TXD0_X100/[2]

RXD0_X100/[2]

RING0_X100/[2]

CTS1_X100

EMERG_RST_X100/[1]

AGND_X100

MICN1_X100

MICP1_X100

MICP2_X100

MICN2_X100

EPN1_X100

EPP1_X100

EPP2_X100

EPN2_X100

VMIC_X100

I2CDAT_X100

SD_0_X100

SD_1_X100

SD_2_X100

SD_3_X100

SPICS_X100

RXD2_GPIO9_X100

TP_ENV_X100

DAC_OUT_X100

ADC1_IN_X100

ADC2_IN_X100

TXD2_GPIO10_X100

SD_WP(GPIO8)_X100

SPIDI_X100

SD_DET(GPIO7)_X100

SD_CMD(GPIO6)_X100

SD_CLK(GPIO5)_X100/[2]

I2CCLK_X100

USC5_X100

USC6_X100

CCIN_X100/[1]

USC4_X100

USC3_X100

USC2_X100

USC1_X100

USC0_X100

SYNC_X100

RXD1_X100

TXD1_X100

RTS1_X100

AGND/[1]

VMIC/[1]

MICN1/[1]

EPP1/[1]

EPN1/[1]

MICP1/[1]

I2CCLK/[2]

I2CDAT/[2]

ADC1/[1]

FSDAI/[1]

RXDAI/[1]

TXDAI/[1]

GPIO8/[1]

GPIO7/[1]

GPIO6/[1]

GPIO5/[1]

GPIO4/[1]

RXD1/[1]

TXD1/[1]

CTS1/[1]

RTS1/[1]

RXD0/[1]

TXD0/[1]

CTS0/[1]

RTS0/[1]

DCD0/[1]

DTR0/[1]

DSR0/[1]

RING0/[1]

EMG_RST/[1]

CCIN/[1]

SCLKDAI/[1]

ON/[1]

ON_MODULE/[1]

X100.BATT+/[2]

RXD0@LS

TXD0@LS

CTS0@LS

RTS0@LS

DCD0@LS

DTR0@LS

RING0@LS

DSR0@LS

CTS1@LS

RTS1@LS

RXD1@LS

TXD1@LS

FTDI_RESET/[2]

V480/[2]

VEXT_BUFF/[2]

USC3@LS

USC2@LS

USC1@LS

USC0@LS

VEXT_MODULE/[1]

VEXT_JUMPER/[2]

VREF/[2]

PWR_IND

VCORE/[1]

BATT+/[2]

GND_DETECT_DSB/[2]

CCCLK2/[1]

CCVCC2/[1]

CCIO2/[1]

CCRST2/[1]

CCIN2/[1]

1LS_OUT_B1

1LS_OUT_B2

2LS_IN_B1

2LS_IN_B2

2LS_OUT_A1

2LS_OUT_A2

1LS_IN_A1

1LS_IN_A2

I2C_DAT_LS/[2]

I2C_CLK_LS/[2]

+3V/[1]

LDO_OUT/[2]

MOD_ON_DET/[1]

IGT_X100/[1]

Änderung

Datum

Nam.

Datum

Name

Bear.
Gepr.

Vers.:

Blatt:

Ers. f.:

Ers. d.:

BG:

GND

VCC

GND

@LS = LEVELSHIFTER

If DevKit is used as
DSB Adapter this pin is low

Control

ASC0.1

ASC0.2

ASC1

DAI

AUDIO2

GPIO

= ENABLE RS232/LEVELSHIFTER*

= ENABLE FTDI ONBOARD

*The equivalent switch on DSB Mini
must be set to RS232

SCLK

RXDDAI

TXDDAI

PINHEADER

80 PIN INTERFACE

PATCHFIELD

LEVEL SHIFTER

POWER INDICATION CICUIT

FREE LEVELSHIFTER PATCHFIELD

FREE LEVELSHIFTER PINHEADER

EEPROM

>A=

>B=

All manuals and user guides at all-guides.com

Summary of Contents for Cinterion LGA

Page 1: ...Cinterion LGA DevKit User Guide Version 03 DocId lga_devkit_ug_v03 All manuals and user guides at all guides com a l l g u i d e s c o m ...

Page 2: ...THE RECIPIENT SHALL NOT COPY MODIFY DISCLOSE OR REPRODUCE THE DOCUMENT EXCEPT AS SPECIFICALLY AUTHORIZED BY THALES Copyright 2020 THALES DIS AIS Deutschland GmbH Trademark Notice Thales the Thales logo are trademarks and service marks of Thales and are registered in certain coun tries Microsoft and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States...

Page 3: ...n Module Start and Power Down 14 4 5 RST Button Module Reset 14 4 6 ASC0 Switch Module UART Interface Selection 14 4 7 PWR Switch Power Source Selection 14 4 8 Free Level Shifters 15 4 9 LEDs 15 4 10 Patch Field 15 4 11 RF Antenna 16 4 12 Power Supply 17 4 12 1 Supply Current Measurement 17 4 12 2 External Reference Supply 18 5 General Characteristics 19 6 Operating the LGA DevKit with a DSB 20 6 ...

Page 4: ... 8 1 Revision History 24 8 2 Related Documents 24 8 3 Safety Precaution Notes 25 8 4 Regulatory Compliance Information 25 9 Appendix 26 9 1 LGA DevKit SM 26 9 1 1 Placement 26 9 1 2 Schematics 27 9 2 LGA DevKit L 30 9 2 1 Placement 30 9 2 2 Schematics 31 9 3 Errata Troubleshooting 34 All manuals and user guides at all guides com ...

Page 5: ... and Benefits LGA DevKit socket supports four different module footprints with different LGA pad counts for industrial industrial plus platform modules With LGA DevKit SM LGA106 LGA114 and LGA120 With LGA DevKit L LGA156 Future proof ready for new upcoming modules Stand alone Get the LGA module up and running without additional tooling Supports DSB75 DSB Mini as port extender UART via USB VCP and ...

Page 6: ...are supported by the LGA DevKit variants SM and L de pending on the module s pad count i e module s footprint Table 1 Supported products LGA DevKit SM LGA DevKit L S LGA 106 LGA 114 M LGA 120 L LGA 156 BGS12 BGS8 PDS5 BGS2 EHS6 PDS6 BGS5 EHS8 PLS62 W EHS5 ELS61 PLS8 ELS31 ELS81 EMS31 Cinterion ENS22 EXS62 EXS82 All manuals and user guides at all guides com a l l g u i d e s c o m ...

Page 7: ... Cinterion LGA DevKit L Ordering number L30960 N0112 A100 Base PCB for the industrial plus platform modules USB and SMA cable An ultra wideband high efficiency antenna A bag of jumpers 25pcs A quick start guide Cinterion LGA DevKit socket SML Ordering number L30960 N0110 A100 The needle socket fitting on both PCB versions SM and L Screws fixing frames retention lid Figure 1 shows the LGA DevKit pa...

Page 8: ...leased Page 8 of 36 Figure 2 LGA DevKit socket SML with LGA DevKit variants SM and L Cinterion LGA DevKit socket SML L30960 N0110 A100 Cinterion LGA DevKit L L30960 N0112 A100 Cinterion LGA DevKit SM L30960 N0111 A100 LGA106 LGA114 LGA120 LGA156 SM L All manuals and user guides at all guides com ...

Page 9: ...ed ERROR LED may indicate issues that should be corrected For de tails see Section 4 9 Note By scanning the QR code at the underside of the LGA DevKit you will also find further information videos and available drivers 2 1 Mounting the LGA DevKit Socket Before operating the socket has to be mounted onto the LGA DevKit with 4 screws Scanning the QR code on the DevKit s underside and or the quick st...

Page 10: ...rint indicators showing the dif ferent LGA module footprints Figure 3 LGA DevKit SM top view Figure 4 LGA DevKit SM underside view Error LED Configurable interruptible signals Adjustable supply Footprint indicator GPS Activity LEDs Channel select Activity LED USB VCP PWR Current test USB PWR Supply mode MAIN DIV MAIN and DIV antenna connectors are interchanged with the LGA DevKit L variant Footpri...

Page 11: ...80Pin DSB75 DSB Mini Connector ASC0 Micro USB NativeMicro USB RF Main DRX Antenna Connector On board Sim Connector Combinded Powering MCU control unit Error detection LED Footprint detection Button ON BTN Button RST BTN USB Data Module Signals Power SIM Antenna ASC0 Signal Module Signals StatusLEDS Power User Interface Connectors Power Block Logical Block Controlling SIM2 Module Signaling Start mo...

Page 12: ...rts should be used to improve power capabilities Note The modem s USB driver can be downloaded from the LGA DevKit s web page that can be reached by scanning the QR code 4 2 SIM On the LGA DevKit s underside you find a SIM card holder that is con nected to the module s regular SIM interface lines except for the CCIN line where the default jumper needs to be set for CCIN at the CONTROL pin headers ...

Page 13: ...ed green in Figure 7 Placing a jumper connects a line through a level shifter to the associated pin at the 2x40 pin connector at the underside of the LGA DevKit and thus to a connected DSB75 DSB Mini See also Figure 5 Not placing a jumper leaves a module signal open External periphery can also be connected to all accessible module signals directly When con necting other external periphery to the p...

Page 14: ...ty is only available if the default jumper is set for EMERG_RST at the CONTROL pin block see Section 4 3 4 6 ASC0 Switch Module UART Interface Selection The ASC0 switch selects the module s UART communication interface either via USB VCP FTDI232R or via RS232 D Sub interface on the DSB75 DSB Mini Changing this from USB to RS232 during operation resets the FTDI VCP bridge in order to release the si...

Page 15: ...cessible close to the patch field as well with the reference Vext and Vref The Vref related lev el shifter connections can also be accessed via four addi tional pads at the left underside of the LGA DevKit where additional pins may be soldered Attention The warranty may be lost if the patch field is sol dered Figure 9 Patch field LED Meaning RED Blinking continuously Module is inserted wrongly ori...

Page 16: ... antenna interfaces have additional ESD protection implemented The LGA DevKit package includes a broad band high efficiency PCB antenna that can be used with the DevKit for all radio band combinations Figure 10 S11 MAIN antenna input return loss transmit direction with socket Figure 11 S21 MAIN antenna insertion loss transmit direction with socket Figure 12 S12 MAIN antenna insertion loss receive ...

Page 17: ... short 2G peak currents up to 2 5A 4 12 1 Supply Current Measurement The LGA DevKit supports three methods to measure the current consumption of the inserted module Measure the voltage across the on board 100 mOhm shunt resistor Measure the current by a current meter Power the module by an external power supply e g power analyzer All options require a jumper placed on the 4th BB and 5th RF row for...

Page 18: ... an external reference voltage connected the interface operates at 3V to meet the DSB75 DSB Mini requirements But if it is required to operate the interface at another voltage an external source in the range between 1 2V 5V can be connected to REF IN and GND as shown in Figure 15 Figure 15 External reference supply and pin header for free level shifter Please note that this jumper should not be se...

Page 19: ...oltage on USB ports 0 3 5 5 V Voltage on DSB port 0 3 5 5 V Voltage on signal pin header depending on used module 0 3 2 1 V Current signal pin header depending on used module 10 10 mA Voltage on external reference 0 3 6 V Socket single contact continues current 2 A Table 3 Operating and environmental conditions Parameter Min Max Unit Recommended operating condition 0 45 C Storage temperature 0 85 ...

Page 20: ... the power on the DSB connector If you select USB the DevKit is powered by its USB ports and the DSB expects a separated power source Use the ASC0 switch to select the first UART If you select RS232 the modules ASC0 is conducted to the DSB and can be accessed on the D SUB connector If you select USB the UART can be accessed via USB VCP port Note that the USB VCP bridge will be in reset state while...

Page 21: ... the following steps Mount the LGA DevKit onto the DSB75 Insert the module Set PWR and ASC0 Check if all jumpers are placed at the pin header CONTROL ASC0_A and PWR Connect the host PC to DSB75 via Sub D Connect power to DSB75 and if needed to the LGA DevKit Press the ON button or the DSB75 IGT button Figure 17 LGA DevKit on DSB75 All manuals and user guides at all guides com a l l g u i d e s c o...

Page 22: ...ain at VDIG pad 10 of the LGA106 foot print Therefore please connect IO25 and VEXT via a jumper 7 2 BGS12 Operation For a proper start of BGS12 a connection between the module s ON signal in Control block and VREF in level shifter block is required 7 3 EMS31 Operation EMS31 V requires a pull up resistor for the SIM interface that is not automatically detected as with other modules In order to acti...

Page 23: ...ates are performed without interruption the default jumper at VEXT at the CONTROL pin header must be removed Instead this jumper needs to be placed at the LEVELSHIFTER pin header to connect VEXT_B and VREF Also with ENS22 the white ON LED blinks only very shortly and about 3 5 seconds before the module actually starts up All manuals and user guides at all guides com ...

Page 24: ...evKit User Guide v02 New document Cinterion LGA DevKit User Guide v01 8 2 Related Documents 1 Hardware Interface Description for your Thales module 2 AT Command Set for your Thales module Chapter What is new 6 1 Added note regarding additional pull up resistor on DSB Mini 7 4 Added remark on ENS22 jumper settings required for firmware updates 9 Added placement and schematics for LGA DevKit L Chapt...

Page 25: ...for evaluation and development purposes only and should therefore only be used in a laboratory test environment The device is not CE ap proved and has not been authorized as required by the rules of the FCC All persons handling the Cinterion LGA DevKit must be properly trained in electronics and observe good engineer ing practice standards Pacemaker patients are advised to keep their hand held mob...

Page 26: ...9 C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C70 C71 C72 C73 C74 C75 C76 C77 C78 CON8 D1 D2 D3 D5 IC1 IC2 IC3 IC4 IC5 IC6 IC 7 IC8 IC9 IC10 IC11 IC14 IC15 IC16 IC17 IC18 IC19 IC20 IC21 IC22 IC99 JP1 JP7 L28 L29 L30 L31 L32 L33L34 L35 LED7 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R27 R28 R29 R30 R31 R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R...

Page 27: ... IC9B GND VCC 18 16 IC9C R87 R88 TP57 TP61 R96 S1 A B R97 T15B R98 TP66 TP75 TP77 TP78 TP79 TP80 VOUT 5 VIN 1 EN 3 GND 2 BP 4 IC11 C75 C76 C77 C78 R99 LED9 R100 R101 D5 R103 CON2 GND GND CON3 GND GND TP4 TP5 TP6 TP10 T17A 5 3 4 T15A GND 2 GND 2 GND 2 ANT_GPS ANT_GPS AGND 3 AGND 3 VMIC 3 VMIC 3 MICN1 3 MICN1 3 EPP1 3 EPP1 3 EPN1 3 EPN1 3 MICP1 3 MICP1 3 I2CCLK 2 I2CCLK 2 I2CDAT 2 I2CDAT 2 ADC1 3 AD...

Page 28: ... T10 T14A T14B R26 T11B T11A JP2 1 2 3 4 5 6 7 8 9 10 FLT 6 DVDT 1 EN UVLO 2 GND 8 2 ILM 7 IN 3 2 OUT 5 T6 3 1 5 4 2 T16 3 1 5 4 2 C57 R57 LED6 R63 IC10 IN 9 2 EN 7 GND 5 2 OUT 1 2 FB 3 SS 6 PB 4 R75 5 3 4 T1A 2 6 1 T1B R76 R77 R78 R79 R80 R81 C73 C74 D2 D1 R84 R85 CON17 P 1 P 2 P 3 P 4 P 5 P 10 P 6 2 P 8 2 P 11 CON18 P 1 P 2 P 3 P 4 P 5 P 10 P 6 2 P 8 2 P 11 R60 R86 R90 R91 R92 T8B R93 R94 R95 TP...

Page 29: ...C B 8 GND 4 C59 C61 C62 C63 C64 C65 C66 JP6 1 2 3 4 5 6 7 8 9 10 11 12 JP7 1 2 3 4 SCL 1 VSS 2 SDA 3 VCC 4 NC 5 TP52 TP53 TP54 TP55 C67 C68 C69 C70 C71 R82 C72 T3A R83 TP59 TP60 T3B R89 TP11 TP12 TP16 TP17 TP18 TP73 TP74 TP82 TP83 D4 RTS0_X100 2 RTS0_X100 2 CTS0_X100 2 CTS0_X100 2 DTR0_X100 2 DTR0_X100 2 DSR0_X100 2 DSR0_X100 2 DCD0_X100 2 DCD0_X100 2 TXD0_X100 2 TXD0_X100 2 RXD0_X100 2 RXD0_X100 ...

Page 30: ...6 C47 C48 C50 C51 C52 C53 C57 C59 C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C70 C71 C72 C73 C74 C75 C76 C77 C78 CON8 D1 D2 D3 D5 IC1 IC2 IC3 IC4 IC5 IC6 IC7 IC9 IC10 IC11 IC14 IC15 IC16 IC17 IC18 IC19 IC20 IC21 IC22 IC99 JP1 JP7 L28 L29 L30 L31 L32 L33 L34 L35 LED7 LED8 PATCHFIELD R1 R2 R3 R4 R5 R6 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R27 R28 R29 R30 R31 R32 R33 R34 R35 R36 R37 R3...

Page 31: ...M P 1 P 2 P 3 P 4 P 5 P 10 P 6 2 P 8 2 P 11 CON17 TP58 R3 JP1 1 2 3 4 LED8 GND 2 GND 2 GND 2 GND 2 ANT_GPS ANT_GPS AGND 3 AGND 3 VMIC 3 VMIC 3 MICN1 3 MICN1 3 EPP1 3 EPP1 3 EPN1 3 EPN1 3 MICP1 3 MICP1 3 I2CCLK 2 I2CCLK 2 I2CDAT 2 I2CDAT 2 ADC1 3 ADC1 3 FSDAI 3 FSDAI 3 RXDAI 3 RXDAI 3 TXDAI 3 TXDAI 3 GPIO8 3 GPIO8 3 GPIO7 3 GPIO7 3 GPIO6 3 GPIO6 3 GPIO5 3 GPIO5 3 GPIO4 3 GPIO4 3 RXD1 3 RXD1 3 RXD1 ...

Page 32: ...5B 2 6 1 3 1 5 4 2 T10 T14A T14B R26 T11B T11A JP2 1 2 3 4 5 6 7 8 9 10 FLT 6 DVDT 1 EN UVLO 2 GND 8 2 ILM 7 IN 3 2 OUT 5 T6 3 1 5 4 2 T16 3 1 5 4 2 C57 R57 LED6 R63 IC10 IN 9 2 EN 7 GND 5 2 OUT 1 2 FB 3 SS 6 PB 4 R75 5 3 4 T1A 2 6 1 T1B R76 R77 R78 R79 R80 R81 C73 C74 D2 D1 R85 CON18 P 1 P 2 P 3 P 4 P 5 P 10 P 6 2 P 8 2 P 11 R60 R86 R90 R91 R92 T8B R93 R94 R95 TP62 TP63 TP64 TP65 TP67 TP68 TP76 T...

Page 33: ... 2 3 4 5 6 7 8 9 10 11 12 JP7 1 2 3 4 SCL 1 VSS 2 SDA 3 VCC 4 NC 5 TP52 TP53 TP54 TP55 C67 C68 C69 C70 C71 R82 C72 T3A R83 TP59 TP60 T3B R89 TP11 TP12 TP16 TP17 TP18 TP73 TP74 TP82 TP83 D4 TP56 TP84 TP85 TP86 TP87 TP88 TP89 TP90 TP91 RTS0_X100 2 RTS0_X100 2 CTS0_X100 2 CTS0_X100 2 DTR0_X100 2 DTR0_X100 2 DSR0_X100 2 DSR0_X100 2 DCD0_X100 2 DCD0_X100 2 TXD0_X100 2 TXD0_X100 2 RXD0_X100 2 RXD0_X100 ...

Page 34: ...n B22 built in a smaller quantity has a limited footprint detec tion Modules with bold lettering QUALCOMM e g EXS81 or wrongly positioned RohS sym bol e g ELS61 81 on the module s underside might be detected as a wrong footprint and will therefore not be powered up This limitation has been improved in conjunction with the socket s module footprint PCB B22 Error LED TXD0 LED The LGA DevKit s PCB re...

Page 35: ...1 shows measurements with the old LGA DevKit socket re garding the S11 DevKit s MAIN antenna module RF path as well as the S21 DevKit s MAIN an tenna RF path loss Measurement results for the new LGA DevKit socket are shown above in Section 4 11 Figure 20 S11 MAIN antenna input return loss transmit direction with old socket Figure 21 S21 MAIN antenna insertion loss transmit direction with old socke...

Page 36: ...herstrasse 81 81541 Munich Germany Thales 2020 All rights reserved Thales the Thales logo are trademarks and service marks of Thales and are registered in certain countries All manuals and user guides at all guides com a l l g u i d e s c o m ...

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