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UART Registers Reference

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SNIU028A – February 2016 – Revised April 2016

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UART Overview

12.7.4 UART Control Register 3 (UARTCTRL3)

Address FFF7D80C – UART 0 Control Register 3

Address FFF7D90C – UART 1 Control Register 3

Figure 12-6. UART Control Register 3 (UARTCTRL3)

SW_RESET

POWERDOWN

CLOCK

RX_INT_ENA

TX_INT_ENA

WAKEUP_INT_

ENA

BRKDT_INT_E

ERR_INT_ENA

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -

= value after reset

Table 12-5. UART Control Register 3 (UARTCTRL3) Register Field Descriptions

Bit

Field

Type

Reset

Description

SW_RESET

R/W

Software reset for UART Transmitter/Receiver

0 = Disables Software Reset (Default)

1 = Enables Software Reset

POWERDOWN

R/W

Power-down Transmitter/Receiver Control

0 = Disables Power-down mode (Default)

1 = Enables Power-down mode

CLOCK

R/W

UART Clock Select

0 = Selects external clock (Default)

1 = Selects internal clock

RX_INT_ENA

R/W

Enables the interrupts from UART Receiver

0 = Disables interrupts from UART Receiver (Default)

1 = Enables interrupts from UART Receiver

TX_INT_ENA

R/W

Enables the interrupts from UART Transmitter

0 = Disables interrupts from UART Transmitter (Default)

1 = Enables interrupts from UART Transmitter

WAKEUP_INT_EN
A

R/W

Enables the wakeup interrupt from UART

0 = Disables Wakeup Interrupt (Default)

1 = Enables Wakeup Interrupt

BRKDT_INT_ENA

R/W

Enables the Broken Circuit interrupt from UART Receiver

0 = Disables Broken Circuit Interrupt (Default)

1 = Enables Broken Circuit Interrupt

ERR_INT_ENA

R/W

Enables UART Receiver Error Interrupt

0 = Disables UART Receiver Error Interrupt (Default)

1 = Enables UART Receiver Error Interrupt

Summary of Contents for UCD3138

Page 1: ...UCD3138 Digital Power Supply Controller Technical Reference Manual Literature Number SNIU028A February 2016 Revised April 2016 ...

Page 2: ...Max 50 2 12 Time Resolution of Various DPWM Registers 51 2 13 PWM Counter and Clocks 53 2 14 DPWM Registers Overview 53 2 15 DPWM Control Register 0 DPWMCTRL0 53 2 15 1 DPWM Auto Config Mid and Max Registers 53 2 15 2 Intra Mux 53 2 15 3 Cycle by Cycle Current Limit Enable 54 2 15 4 Multi Mode On Off 56 2 15 5 Minimum Duty Mode 56 2 15 6 Master Sync Control Select 58 2 15 7 Master Sync Slave Enabl...

Page 3: ...witching Interrupt Bits 65 2 24 3 INT Bit 65 2 25 DPWM Counter Preset Register 65 2 26 Blanking Registers 65 2 27 DPWM Adaptive Sample Register 66 2 28 DPWM Fault Status Register 66 2 29 DPWM Auto Switch Registers 66 2 30 DPWM Edge PWM Generation Register 66 2 31 DPWM 0 3 Registers Reference 66 2 31 1 DPWM Control Register 0 DPWMCTRL0 66 2 31 2 DPWM Control Register 1 DPWMCTRL1 70 2 31 3 DPWM Cont...

Page 4: ...3 1 2 EADC Error Output 113 3 1 3 EADC Triggering EADC Output to Filter 115 3 1 4 EADC Timing 115 3 1 5 EADC Averaging 116 3 1 6 Enabling EADC and Front End 117 3 2 Front End DAC 118 3 3 Ramp Module 119 3 3 1 DAC Ramp Overview 119 3 3 2 DAC Ramp Start and End Points 119 3 3 3 DAC Ramp Steps 120 3 3 4 DAC Ramp Start Interrupts Start Delay 121 3 3 5 RAMPSTAT Register 121 3 3 6 DAC RAMP when EADC is ...

Page 5: ...tput Multiplier 151 4 3 12 Period Multiplier Select 151 4 3 13 Ki Adder Mode 151 4 4 XN YN Read and Write Registers 152 4 4 1 CPU Xn Register 152 4 4 2 Filter XN Read Register 152 4 4 3 Filter YN Read Registers 152 4 5 Coefficient Configuration Register 153 4 6 Kp Ki and Kd Registers 155 4 7 Alpha Registers 155 4 8 Filter Nonlinear Limit Registers 155 4 9 Clamp Registers 156 4 10 Filter Preset Reg...

Page 6: ...12 Analog Peak Current Mode 190 5 13 Automatic Cycle Adjustment 190 5 13 1 Calculation 190 5 13 2 Configuration 191 5 13 3 Scaling 191 5 14 Loop Mux Registers Reference 191 5 14 1 Front End Control 0 Mux Register FECTRL0MUX 191 5 14 2 Front End Control 1 Mux Register FECTRL1MUX 193 5 14 3 Front End Control 2 Mux Register FECTRL2MUX 195 5 14 4 Sample Trigger Control Register SAMPTRIGCTRL 197 5 14 5...

Page 7: ...ister ACOMPCTRL1 237 6 11 3 Analog Comparator Control 2 Register ACOMPCTRL2 239 6 11 4 Analog Comparator Control 3 Register ACOMPCTRL3 241 6 11 5 External Fault Control Register EXTFAULTCTRL 242 6 11 6 Fault Mux Interrupt Status Register FAULTMUXINTSTAT 243 6 11 7 Fault Mux Raw Status Register FAULTMUXRAWSTAT 245 6 11 8 Comparator Ramp Control 0 Register COMPRAMP0 247 6 11 9 Digital Comparator Con...

Page 8: ...e to Crosstalk 302 8 6 ADC12 Control FSM 302 8 7 Conversion 302 8 8 Sequencing 303 8 9 Digital Comparators 304 8 10 ADC Averaging 305 8 11 Temperature Sensor 305 8 12 Temp Sensor Control Register TEMPSENCTRL 306 8 13 PMBus Addressing 307 8 13 1 PMBus Control Register 3 PMBCTRL3 307 8 14 Dual Sample and Hold 308 8 14 1 ADC Control Register ADCCTRL 309 8 15 Usage of Sample and Hold Circuitry for Hig...

Page 9: ...3 Global I O Open Drain Control Register GLBIOOD 348 9 12 4 Global I O Value Register GLBIOVAL 349 9 12 5 Global I O Read Register GLBIOREAD 350 9 13 Trim and Test Registers Note 351 9 13 1 Clock Trim Register CLKTRIM For Factory Test Use Only Except HFO_LN_FILTER_EN 351 10 PMBus Interface I2C Interface 352 10 1 PMBus Register Summary 353 10 2 PMBus Slave Mode Initialization 353 10 2 1 Initializat...

Page 10: ...PMBCTRL1 382 10 10 2 PMBus Transmit Data Buffer PMBTXBUF 384 10 10 3 PMBus Receive Data Register PMBRXBUF 385 10 10 4 PMBus Acknowledge Register PMBACK 386 10 10 5 PMBus Status Register PMBST 387 10 10 6 PMBus Interrupt Mask Register PMBINTM 389 10 10 7 PMBus Control Register 2 PMBCTRL2 390 10 10 8 PMBus Hold Slave Address Register PMBHSA 392 10 10 9 PMBus Control Register 3 PMBCTRL3 393 11 Timer ...

Page 11: ...hronous Timing Mode 422 12 3 UART Interrupts 423 12 4 Transmit Interrupt 424 12 5 Receive Interrupt 424 12 6 Error Interrupts 424 12 7 UART Registers Reference 426 12 7 1 UART Control Register 0 UARTCTRL0 426 12 7 2 UART Receive Status Register UARTRXST 427 12 7 3 UART Transmit Status Register UARTTXST 428 12 7 4 UART Control Register 3 UARTCTRL3 429 12 7 5 UART Interrupt Status Register UARTINTST...

Page 12: ...MCTRL 468 15 1 2 Write Control Register WCTRL 470 15 1 3 Peripheral Control Register PCTRL 471 15 1 4 Peripheral Location Register PLOC 472 15 1 5 Peripheral Protection Register PPROT 473 15 2 DEC Address Manager Registers Reference 473 15 2 1 Memory Fine Base Address High Register 0 MFBAHR0 473 15 2 2 Memory Fine Base Address Low Register 0 MFBALR0 475 15 2 3 1 1 1 Memory Fine Base Address High R...

Page 13: ...6 4 1 Interrupt Handling by CPU 504 16 4 2 Interrupt Generation at Peripheral 504 16 4 3 CIM Interrupt Management CIM 504 16 4 4 CIM Input Channel Management 505 16 4 5 CIM Prioritization 506 16 4 6 CIM Operation 506 16 4 7 Register Map 508 16 5 SYS System Module Registers Reference 508 16 5 1 Clock Control Register CLKCNTL 508 16 5 2 System Exception Control Register SYSECR 510 16 5 3 System Exce...

Page 14: ...e Examples 523 17 5 1 Checksum Clearing 523 17 5 2 Erasing Flash 524 17 5 3 Serial Port Based Backdoor 524 17 5 4 I O Line Based Back Door 524 18 CIM Central Interrupt Module Registers Reference 525 18 1 IRQ Index Offset Vector Register IRQIVEC 526 18 2 FIQ Index Offset Vector Register FIQIVEC 527 18 3 FIQ IRQ Program Control Register FIRQPR 528 18 4 Pending Interrupt Read Location Register INTREQ...

Page 15: ... 78 2 24 DPWM Event 4 Register DPWMEV4 79 2 25 DPWM Sample Trigger 1 Register DPWMSAMPTRIG1 80 2 26 DPWM Sample Trigger 2 Register DPWMSAMPTRIG2 81 2 27 DPWM Phase Trigger Register DPWMPHASETRIG 82 2 28 DPWM Cycle Adjust A Register DPWMCYCADJA 83 2 29 DPWM Cycle Adjust B Register DPWMCYCADJB 84 2 30 DPWM Resonant Duty Register DPWMRESDUTY 85 2 31 DPWM Fault Control Register DPWMFLTCTRL 86 2 32 DPW...

Page 16: ...P 130 3 15 DAC Saturation Step Register DACSATSTEP 131 3 16 EADC Trim Register EADCTRIM 132 3 17 EADC Control Register EADCCTRL 133 3 18 Analog Control Register ACTRL 135 3 19 Pre Bias Control Register 0 PREBIASCTRL0 136 3 20 Pre Bias Control Register 1 PREBIASCTRL1 137 3 21 SAR Control Register SARCTRL 138 3 22 SAR Timing Register SARTIMING 139 3 23 EADC Value Register EADCVALUE 140 3 24 EADC Raw...

Page 17: ...ister FILTERKCOMPB 202 5 10 DPWM Mux Register DPWMMUX 203 5 11 Constant Power Control Register CPCTRL 205 5 12 Constant Power Nominal Threshold Register CPNOM 207 5 13 Constant Power Max Threshold Register CPMAX 208 5 14 Constant Power Configuration Register CPCONFIG 209 5 15 Constant Power Max Power Register CPMAXPWR 210 5 16 Constant Power Integrator Threshold Register CPINTTHRESH 211 5 17 Const...

Page 18: ...1 6 27 DPWM 3 Current Limit Control Register DPWM3CLIM 274 6 28 DPWM 3 Fault AB Detection Register DPWM3FLTABDET 276 6 29 DPWM 3 Fault Detection Register DPWM3FAULTDET 278 6 30 HFO Fail Detect Register HFOFAILDET 281 6 31 LFO Fail Detect Register LFOFAILDET 282 6 32 IDE Control Register IDECTRL 283 7 1 Fault IO Direction Register FAULTDIR 285 7 2 Fault Input Register FAULTIN 286 7 3 Fault Output R...

Page 19: ...Register ADCAVGCTRL 331 9 1 334 9 2 335 9 3 336 9 4 Package ID Register PKGID 336 9 5 Brownout Register BROWNOUT 337 9 6 Temp Sensor Control Register TEMPSENCTRL 338 9 7 I O Mux Control Register IOMUX 339 9 8 Current Sharing Control Register CSCTRL 340 9 9 Temperature Reference Register TEMPREF 341 9 10 Power Disable Control Register PWRDISCTRL 342 9 11 Global I O EN Register GBIOEN 346 9 12 Globa...

Page 20: ...PEC Byte 377 10 38 Block Write with PEC Byte 377 10 39 Block Read w o PEC Byte 378 10 40 Block Read with PEC Byte 378 10 41 Block Write Block Read Process Call w o PEC Byte 379 10 42 Block Write Block Read Process Call with PEC Byte 379 10 43 Alert Response 379 10 44 Extended Command Write Byte w o PEC Byte 380 10 45 Extended Command Write Byte with PEC Byte 380 10 46 Extended Command Write Word w...

Page 21: ...TTXST 428 12 6 UART Control Register 3 UARTCTRL3 429 12 7 UART Interrupt Status Register UARTINTST 430 12 8 UART Baud Divisor High Byte Register UARTHBAUD 431 12 9 UART Baud Divisor Middle Byte Register UARTMBAUD 432 12 10 UART Baud Divisor Low Byte Register UARTLBAUD 433 12 11 UART Receive Buffer UARTRXBUF 434 12 12 UART Transmit Buffer UARTTXBUF 435 12 13 UART I O Control Register UARTIOCTRLSCLK...

Page 22: ...dress High Register 15 MFBAHR15 491 15 23 Memory Fine Base Address High Register 16 MFBAHR16 492 15 24 Program Flash Control Register PFLASHCTRL 493 15 25 Data Flash Control Register DFLASHCTRL 494 15 26 Flash Interlock Register FLASHILOCK 495 16 1 498 16 2 Base Address 499 16 3 505 16 4 Clock Control Register CLKCNTL 508 16 5 System Exception Control Register SYSECR 510 16 6 System Exception Stat...

Page 23: ...ter DPWMOVERFLOW Register Field Descriptions 87 2 22 DPWM Interrupt Register DPWMINT Register Field Descriptions 88 2 23 DPWM Counter Preset Register DPWMCNTPRE Register Field Descriptions 90 2 24 DPWM Blanking A Begin Register DPWMBLKABEG Register Field Descriptions 91 2 25 DPWM Blanking A End Register DPWMBLKAEND Register Field Descriptions 92 2 26 DPWM Blanking B Begin Register DPWMBLKBBEG Regi...

Page 24: ...ficient 0 Register FILTERKPCOEF0 Register Field Descriptions 168 4 10 Filter KP Coefficient 1 Register FILTERKPCOEF1 Register Field Descriptions 169 4 11 Filter KI Coefficient 0 Register FILTERKICOEF0 Register Field Descriptions 170 4 12 Filter KI Coefficient 1 Register FILTERKICOEF1 Register Field Descriptions 171 4 13 Filter KD Coefficient 0 Register FILTERKDCOEF0 Register Field Descriptions 172...

Page 25: ...criptions 237 6 3 Analog Comparator Control 2 Register ACOMPCTRL2 Register Field Descriptions 239 6 4 Analog Comparator Control 3 Register ACOMPCTRL3 Register Field Descriptions 241 6 5 External Fault Control Register EXTFAULTCTRL Register Field Descriptions 242 6 6 Fault Mux Interrupt Status Register FAULTMUXINTSTAT Register Field Descriptions 243 6 7 Fault Mux Raw Status Register FAULTMUXRAWSTAT...

Page 26: ...CSEQSEL1 Register Field Descriptions 321 8 10 ADC Sequence Select Register 2 ADCSEQSEL2 Register Field Descriptions 322 8 11 ADC Sequence Select Register 3 ADCSEQSEL3 Register Field Descriptions 323 8 12 ADC Result Registers 0 15 ADCRESULTx x 0 15 Register Field Descriptions 324 8 13 ADC Averaged Result Registers 0 5 ADCAVGRESULTx x 0 15 Register Field Descriptions 325 8 14 ADC Digital Compare Lim...

Page 27: ...Compare Channel 0 Control Register T24CMPCTRL0 Register Field Descriptions 412 11 9 24 bit Output Compare Channel 1 Control Register T24CMPCTRL1 Register Field Descriptions 413 11 10 PWMx Counter Data Register T16PWMxCNTDAT Register Field Descriptions 414 11 11 PWMx Counter Control Register T16PWMxCNTCTRL Register Field Descriptions 415 11 12 PWMx 16 bit Compare Channel 0 1 Data Register T16PWMxCM...

Page 28: ...7 Register Field Descriptions 483 15 19 Memory Fine Base Address High Register 8 MFBAHR8 Register Field Descriptions 484 15 20 Memory Fine Base Address High Register 9 MFBAHR9 Register Field Descriptions 485 15 21 Memory Fine Base Address High Register 10 MFBAHR10 Register Field Descriptions 486 15 22 Memory Fine Base Address High Register 11 MFBAHR11 Register Field Descriptions 487 15 23 Memory F...

Page 29: ...pyright 2016 Texas Instruments Incorporated List of Tables 18 3 FIQ IRQ Program Control Register FIRQPR Register Field Descriptions 528 18 4 Pending Interrupt Read Location Register INTREQ Register Field Descriptions 529 18 5 Interrupt Mask Register REQMASK Register Field Descriptions 530 ...

Page 30: ...unications ports In terms of memory UCD3138 offers 32KB of program flash 2kB of data flash 4KB RAM and 4KB of ROM 1 1 Scope of This Document For the most up to date product specifications please consult the UCD3138 Device datasheet SLUSAP2 available at www ti com 1 2 A Guide to Other Documentation for all Members of UCD3138 Family of Products All members of UCD3138 family of Controllers share the ...

Page 31: ...D8 Timers Low res PWM Watchdog capture compare SLUU996 Central Interrupt Module CIM SLUU994 SLUUB54 ARM Core SLUU994 ROM bootloader SLUU994 SLUUAD8 SLUUB54 Flash Flash Interlock key PFLASH DFLASH SLUU994 SLUUAD8 SLUUB54 MMC Memory Controller SLUU994 DEC Address Manager SLUU994 SYS System Module Software reset Exception status Clock Control M_DIV_RATIO DEV device identification SLUU994 SLUUAD8 SLUU...

Page 32: ... UCD3138 device supports multiple sets of the Digital Power Peripherals affording the ability to control upto 3 feedback loops voltage or current and drive 8 outputs simultaneously To inter connect all the DPPs there is a large module called the Loop Mux This permits a high degree of flexibility in DPP configuration Any Front End can be connected to any Filter and any Filter output can be connecte...

Page 33: ... supply topologies Each DPWM module has two output pins DPWMxA and DPWMxB x 0 1 2 3 The DPWM provides for programmable dead times and cycle adjustments for current balancing between phases It controls the triggering of the EADC It can synchronize to other DPWMs or to external sources Alternately it can provide synchronization information to other DPWMs or to external recipients The DPWM can also b...

Page 34: ...ge Generation IntraMax 50 2 12 Time Resolution of Various DPWM Registers 51 2 13 PWM Counter and Clocks 53 2 14 DPWM Registers Overview 53 2 15 DPWM Control Register 0 DPWMCTRL0 53 2 16 DPWM Control Register 1 59 2 17 DPWM Control Register 2 62 2 18 Period and Event Registers 64 2 19 Phase Trigger Registers 64 2 20 Cycle Adjust Registers 64 2 21 Resonant Duty Register 64 2 22 DPWM Fault Control Re...

Page 35: ...s next It shuts off the DPWM signals if a fault occurs After the DPWM signals come from the Fault Module DPWMx_F x A B C they are sent to other DPWM Modules The Edge Generation and Intra Mux modules can combine signals from several DPWMs to generate new signals DWMx_E DPWMx_I x A B C The notation of DPWMx_T DPWMx_F where x A B C etc is very useful here to understand the origin and relationship bet...

Page 36: ... ti com 36 SNIU028A February 2016 Revised April 2016 Submit Documentation Feedback Copyright 2016 Texas Instruments Incorporated Digital Pulse Width Modulator DPWM Figure 2 2 Block Diagram of Timing Module in the DPWM module ...

Page 37: ...and pulse spacing are controlled by these clocks giving a resolution of 250 picoseconds The edges generated by these clocks are hence referred to as High Resolution in the illustrations throughout this section Most of the signals out of the DPWM are fairly simple The only complex signals are DPWMA and DPWMB These vary depending upon the power supply topology and are the most important signals comi...

Page 38: ...gnals are used to trigger the Front End to sample input signals The Blanking signals are used to blank fault measurements during noisy events such as FET turn on and turn off This prevents false detection of faults caused by noise They only affect the Cycle By Cycle CBC module Other faults are not blanked Note that Sample Trigger 1 and 2 Blanking A and B and Phase Trigger are shown at logical loca...

Page 39: ...k Copyright 2016 Texas Instruments Incorporated Digital Pulse Width Modulator DPWM 2 3 DPWM Normal Mode Note that Sample Trigger 1 and 2 Blanking A and B and Phase Trigger are shown at logical locations for this specific mode but they can be placed anywhere within the period Figure 2 4 DPWM Normal Mode ...

Page 40: ...ternal delays such as FET and gate driver turn on times The Blanking signals are used to disable the CBC fault signal during noise Generally the noise is caused by DPWM edges The Blanking registers hold fixed values so they are easiest to use with fixed edges rather than with edges that change dynamically So in this case the rising edge of DPWM A and the falling edge of DPWM B are easy to provide ...

Page 41: ...PWM 2 4 DPWM Phase Shift Mode In most modes it is possible to synchronize multiple DPWM modules using the phase shift signal The phase shift signal has two possible sources It can come from the Phase Shift Register or from the Filter Duty value The Phase Shift Register provides a fixed value which is useful in simple multiphase systems such as interleaved PFC When the Filter Duty is the source the...

Page 42: ...dulator DPWM 2 5 DPWM Multiple Output Mode Multi Mode Multi Mode is used for systems where each phase has only one driver signal requirement In this mode each DPWM peripheral can drive two phases with the same pulse width but with a time offset between the phases and with different cycle adjusts for each phase Here is a diagram for Multi mode Figure 2 6 DPWM Multiple Output Mode Multi Mode ...

Page 43: ... Blanking B works only on the falling edge of B And of course Cycle Adjust B is usable on DPWM B There is no restriction preventing the two signals from overlapping each other The diagram shows the two signals 180 degrees out of phase but this is not required They could be 90 degrees 60 degrees or whatever offset is desired 2 6 DPWM Resonant Mode The resonant mode operation depends on the status o...

Page 44: ...ilter Duty Average Dead Time Adaptive Sample Trigger A Event 1 Filter Duty Adaptive Sample Register Adaptive Sample Trigger B Event 1 Filter Duty 2 Adaptive Sample Register DPWM B Rising Edge Event 1 Filter Duty Average Dead Time Event 3 Event 2 DPWM B Falling Edge Filter Period Period Register Event 4 Phase Trigger Phase Trigger Register value or Filter Duty Events always set by their registers r...

Page 45: ... of the two dead times is subtracted from the Filter Duty for both DPWM pins Therefore both pins will have the same on time and the dead times will be fixed regardless of the period The only edge which is fixed relative to the start of the period is the rising edge of DPWM A Blanking A and Blanking B both work only on DPWMA 2 7 Triangular Mode Triangular mode provides a very stable phase shift in ...

Page 46: ...d sample trigger exactly in the center of the On time because the center of the on time does not move in this mode Both Blanking A and Blanking B are applied to DPWMB 2 8 DPWM Leading Edge Mode Leading edge mode is very similar to Normal mode reversed in time The DPWM A falling edge is fixed and the rising edge moves to the left or backwards in time as the filter output increases The DPWMB falling...

Page 47: ...irmware measures Vin and Vout and calculates Kd For example for a Buck topology Kd Vin Vout Vout where Da is duty cycle of the control FET Db is duty cycle of SR FET Vin is input voltage and Vout is output voltage The firmware periodically measures the slowly changing Vin and Vout and puts the calculated result into the Kd register The DPWM hardware adjusts Db every switching cycle maintaining pro...

Page 48: ...t power a pulse width modulated mode Multi Mode is used As power increases and frequency decreases Resonant mode is used As the frequency gets still lower resonant mode is still used however the Sync FET driver changes so that the on time is fixed and does not increase SR Pulse Width is clamped Here are the waveforms for the LLC Figure 2 11 Resonant LLC implementation in UCD3138 with Automatic Mod...

Page 49: ...Mechanism for Automatic Mode Switching in UCD3138 As shown the registers are used in pairs for hysteresis The transition from Control Register 1 to Auto Config Mid only takes place when the Filter Duty goes above the Low Upper threshold It does not go back to Control Register 1 until the Low Lower Threshold is passed This prevents oscillation between modes if the filter duty is close to a mode swi...

Page 50: ...to generate edges for two outputs For DPWM3 the DPWM0 is considered to be the next DPWM Each edge rising and falling for DPWMA and DPWMB has 8 options which can cause it The options are 0 DPWM n A Rising edge 1 DPWM n A Falling edge 2 DPWM n B Rising edge 3 DPWM n B Falling edge 4 DPWM n 1 A Rising edge 5 DPWM n 1 A Falling edge 6 DPWM n 1 B Rising edge 7 DPWM n 1 B Falling edge The Edge Gen is co...

Page 51: ...count the impact of the Edge Gen and IntraMux units Also the GPIO_A_EN GPIO_B_EN bits inside the DPWMCTRL1 register affect the signal state before the IntraMux unit So if these bits are meant to be used to turn the DPWM output off the bits in the original DPWM are supposed to be altered And not the bits in the DPWM module that the outputs are redirected through 2 12 Time Resolution of Various DPWM...

Page 52: ...00_0011_0100_0001 0000 The Sample Trigger registers ignore the 6 least significant bits as shown here Table 2 3 DPWM Sample Trigger 1 Register DPWMSAMPTRIG1 Bit Number 17 6 5 0 Bit Name SAMPLE_TRIGGER RESERVED Access R W Default 0000_0010_0000 00_0000 Only the Event 2 3 and 4 registers use all 18 bits of the field as shown below Table 2 4 DPWM Event 2 Register DPWMEV2 Event 3 and 4 are the same Cy...

Page 53: ...tervals nominally 250 picoseconds long The extra 4 bits representing these intervals are called high resolution bits 2 14 DPWM Registers Overview This section discusses each DPWM register with examples of their use where appropriate In addition it interacts with many other peripherals parts of which are also described below 2 15 DPWM Control Register 0 DPWMCTRL0 The DPWM Control Register 0 is one ...

Page 54: ... effects in different modes Here are the effects Normal Mode In normal mode a CBC event will cause DPWMA to go low before the time dictated by the CLA The dead time for DPWMB will be preserved so the rising edge of DPWMB will be moved forward by the same amount as the falling edge of DPWMA There are only two options for setting the CBC bits in normal mode 1 All cleared no CBC 2 Set both CBC_PWM_AB...

Page 55: ...n needs to be followed by an equal length on time on the other DPWM pin to prevent an offset from building up in a capacitor or inductor In this case it is possible to enable duty cycle matching in these two modes If DPWMA or DPWMB is cut short by a CBC event the next pulse on the other DPWM pin will also be shortened to the same length Here are the states for resonant and multi modes All cleared ...

Page 56: ...uld not be set If the bit is cleared the on time of the DPWM pin is controlled by the Filter output If the bit is set then the on time is controlled by the Event registers The AMS registers only have MULTI_MODE_CLA_B_OFF they do not have MULTI_MODE_CLA_A_OFF 2 15 5 Minimum Duty Mode The MIN_DUTY_MODE bits select how the DPWM handles minimum duty cycle limits 0 Default Filter output is passed direc...

Page 57: ...0 40 60 80 100 120 0 10 20 30 40 50 60 70 80 90 100 Filter Duty Output Duty going down to zero coming up from zero www ti com DPWM Control Register 0 DPWMCTRL0 57 SNIU028A February 2016 Revised April 2016 Submit Documentation Feedback Copyright 2016 Texas Instruments Incorporated Digital Pulse Width Modulator DPWM Figure 2 15 Minimum Duty Mode 1 Figure 2 16 Minimum Duty Mode 2 ...

Page 58: ...Duty increases If the D_ENABLE bit is set however the Filter Duty is subtracted from the period register In this case as the Filter Duty increases from zero to full range the on time will decrease from 100 of the period to 0 of the period This bit is not duplicated in the AMS registers 2 15 9 Resonant Mode Fixed Duty Enable The RESON_MODE_FIXED_DUTY_EN bit only controls the duty cycle width in the...

Page 59: ...ise the DPWM output comes from the DPWM registers only This bit is duplicated in the AMS registers The filter which controls each DPWM is selected by the DPWMx_FILTER_SEL bit in the DPWMMUX register in the Loop Mux 2 15 15 DPWM Enable The PWM_EN bit when set enables the DPWM channel If it is 0 default the DPWM outputs are set to the value in the DPWM Fault Polarity bits Section 2 15 10 Note that i...

Page 60: ...led by this DPWM can be balanced with the current controlled by another DPWM in the same UCD3138 For more information see the Current Balancing section 2 16 5 1 16 5 Sync Out Divisor Selection The SYNC_OUT_DIV_SEL bit field selects a divisor generating the sync out pulse on the external sync out pin It is only effective on the sync out not on internal chip sync signals sent to other DPWMs The divi...

Page 61: ... Please refer to the reference firmware code provided with UCD3138 EVMs for specific guidance regarding each topology 2 16 11 Check Override The CHECK_OVERRIDE bit when set overrides the internal DPWM checking The DPWM checking will prevent invalid placement of Event settings period settings or invalid configurations Setting this bit may be necessary for some topologies 2 16 12 Global Period Enabl...

Page 62: ... can be used for example when measuring input voltage on an isolated supply To use Single Frame enable first initialize the DPWM module and set the SFRAME_EN bit and enable the DPWM globally To actually start the single frame set the PWM_EN bit This will trigger a single frame 2 17 DPWM Control Register 2 The DPWMCTRL2 register like the other 2 control registers has a wide selection of bit fields ...

Page 63: ...ed in time starting at the start of the period and with the last sample at the Sample Trigger 1 point The values are 0 1 sample at the sample trigger time 1 1 sample at 1 2 of the sample trigger time and one at the sample trigger time 2 4 samples at 1 4 1 2 3 4 and full sample trigger time 3 8 samples at 1 8 1 4 3 8 1 2 5 8 3 4 7 8 and full sample trigger Sample trigger 1 can be used either to tri...

Page 64: ... have different effects in different modes see the DPWM Mode sections above They are signed high resolution registers so that the duty can be increased or decreased from the Filter value They only have 16 bits so they cannot adjust the full 18 bit range of the DPWM But their range is still 8 milliseconds which is typically more than a whole switching period High resolution is 250 picosec and the r...

Page 65: ... Switch Registers for more detail on Mode Switching MODE_SWITCH goes high when the DPWM has switched modes MODE_SWITCH_INT_EN enables this interrupt A rising edge on MODE_SWITCH_FLAG_CLR clears the MODE_SWITCH bit This bit is not auto cleared so it will be necessary to clear it with firmware before the next rising edge 2 24 3 INT Bit The INT bit shows that one or more of the interrupt flags is set...

Page 66: ...ng lines can have hysteresis The three registers are DPWMCTRL0 AUTOCONFIGMID AUTOCONFIGMAX If the Filter input to the DPWM goes above DLWMAUTOSWIHIUPTHRESH then the AUTOCONFIGMAX register is used until the Filter input goes below the DPWMAUTOSWIHILOWTHRESH register value Below this value the AUTOCINFIGMID control bits are used until the Filter value goes below DPWMAUTOSWILOLOWTHRESH Below this val...

Page 67: ...ls post edge generation 0 Pass through Default 1 Edge gen output this module 2 PWM C this module 3 Crossover this module 4 Pass through below A 5 Pass through below B 6 Pass through below C 7 Pass through below level 2 C 8 Pass through below level 3 C 27 24 PWM_A_INTR4 _MUX R W 0000 Combines DPWM signals are prior to HR module 0 Pass through Default 1 Edge gen output this module 2 PWM C this modul...

Page 68: ...Mode current channel will be slaved from corresponding channel 14 D_ENABLE R W 0 Converts CLA duty value to DPWM as period CLA duty value 0 Value used for event calculations if CLA Duty Default 1 Value used for event calculations is period minus CLA duty value 13 CBC_SYNC_CUR _LIMIT_EN R W 0 Sets how current limit affects slave sync 0 Slave sync is unaffected during current limit Default 1 Slave s...

Page 69: ...ntinued Bit Field Type Reset Description 3 PWM_B_INV R W 0 PWM B Output Polarity Control 0 Non inverted PWM B output Default 1 Inverts PWM B output 2 PWM_A_INV R W 0 PWM A Output Polarity Control 0 Non inverted PWM A output Default 1 Inverted PWM A output 1 CLA_EN R W 1 CLA Processing Enable 0 Generate PWM waveforms from PWM Register values 1 Enable CLA input Default 0 PWM_EN R W 0 PWM Processing ...

Page 70: ...T _DIS PWM_A_PROT _DIS HIRES_SCALE ALL_PHASE _CLK_ENA HIRES_DIS R W 0 R W 0 R W 0 R W 0 R W 00 R W 1 R W 0 LEGEND R W Read Write R Read only n value after reset Table 2 7 DPWM Control Register 1 DPWMCTRL1 Register Field Descriptions Bit Field Type Reset Description 31 PRESET_EN R W 0 Counter Preset Enable 0 Counter reset to 0 upon detection of sync Default 1 Counter preset to Preset Count Value up...

Page 71: ...ed anytime 01 Events updated at End of Period Default 10 Events updated at count value equal to Sample Trigger 2 register 11 Events updated at End of Period and Sample Trigger 2 position 15 CHECK _OVERRIDE R W 0 PWM Check Override 0 DPWM checks mathematical settings within module correct placement of Event settings period settings Invalid configurations are not allowed 1 Overrides checking for inv...

Page 72: ...to turn off PWM B Output Default 1 Disables asynchronous protection from turning off PWM B Output 4 PWM_A_PROT _DIS R W 0 PWM A Asynchronous Protection Disable 0 Allows asynchronous protection to turn off PWM A Output Default 1 Disables asynchronous protection from turning off PWM A Output 3 2 HIRES_SCALE R W 00 Determines resolution of high resolution steps 00 Resolution of 16 phases Full resolut...

Page 73: ...input of the Filter Settings of 0 and 1 enable the 16 bit signed value of the Resonant Duty register to be added to the Filter Period value for period adjustment in resonant mode 0 PWM Period Register Default 1 Event 2 2 DPWM Resonant Duty Register Bits 13 0 7 IDE_DUTY_B_EN R W 0 IDE Duty Cycle Side B Enable 0 Disabled Default 1 Enabled 6 Reserved R 0 5 4 SAMPLE_TRIG1 _OVERSAMPLE R W 00 Oversample...

Page 74: ...tal Pulse Width Modulator DPWM Table 2 8 DPWM Control Register 2 DPWMCTRL2 Register Field Descriptions continued Bit Field Type Reset Description 1 SAMPLE_TRIG_2 _EN R W 0 Sample Trigger 2 Enable 0 Disable Sample Trigger 2 Default 1 Enable Sample Trigger 2 0 SAMPLE_TRIG_1 _EN R W 1 Sample Trigger 1 Enable 0 Disable Sample Trigger 1 1 Enable Sample Trigger 1 Default ...

Page 75: ... Address 0007000C DPWM 2 Period Register Address 000A000C DPWM 1 Period Register Address 000D000C DPWM 0 Period Register Figure 2 20 DPWM Period Register DPWMPRD 17 4 3 0 PRD Reserved R W 00 0011 0100 0001 R 0 LEGEND R W Read Write R Read only n value after reset Table 2 9 DPWM Period Register DPWMPRD Register Field Descriptions Bit Field Type Reset Description 17 4 PRD R W 00 0011 0100 0001 PWM P...

Page 76: ...10 DPWM 2 Event 1 Register Address 000A0010 DPWM 1 Event 1 Register Address 000D0010 DPWM 0 Event 1 Register Figure 2 21 DPWM Event 1 Register DPWMEV1 17 4 3 0 EVENT1 Reserved R W 00 0000 0001 0100 R 0 LEGEND R W Read Write R Read only n value after reset Table 2 10 DPWM Event 1 Register DPWMEV1 Register Field Descriptions Bit Field Type Reset Description 17 4 EVENT1 R W 00 0000 0001 0100 Configur...

Page 77: ...M 1 Event 2 Register Address 000D0014 DPWM 0 Event 2 Register Figure 2 22 DPWM Event 2 Register DPWMEV2 17 0 EVENT2 R W 0 0000 0011 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 2 11 DPWM Event 2 Register DPWMEV2 Register Field Descriptions Bit Field Type Reset Description 17 0 EVENT2 R W 0 0000 0011 0000 0000 Configures the location of Event 2 Value equals number of PCLK c...

Page 78: ...ter Address 000A0018 Loop 2 DPWM Event 3 Register Address 000D0018 Loop 1 DPWM Event 3 Register Figure 2 23 DPWM Event 3 Register DPWMEV3 17 0 EVENT3 R W 00 0000 0011 1110 0000 LEGEND R W Read Write R Read only n value after reset Table 2 12 DPWM Event 3 Register DPWMEV3 Register Field Descriptions Bit Field Type Reset Description 17 0 EVENT3 R W 00 0000 0011 1110 0000 Configures the location of E...

Page 79: ...ter Address 000A001C Loop 2 DPWM Event 4 Register Address 000D001C Loop 1 DPWM Event 4 Register Figure 2 24 DPWM Event 4 Register DPWMEV4 17 0 EVENT4 R W 00 0000 0111 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 2 13 DPWM Event 4 Register DPWMEV4 Register Field Descriptions Bit Field Type Reset Description 17 0 EVENT4 R W 00 0000 0111 0000 0000 Configures the location of E...

Page 80: ...ddress 000D0020 DPWM 0 Sample Trigger 1 Register Figure 2 25 DPWM Sample Trigger 1 Register DPWMSAMPTRIG1 17 6 5 0 SAMPLE_TRIGGER Reserved R W 0000 0010 0000 R 00 0000 LEGEND R W Read Write R Read only n value after reset Table 2 14 DPWM Sample Trigger 1 Register DPWMSAMPTRIG1 Register Field Descriptions Bit Field Type Reset Description 17 6 SAMPLE_ TRIGGER R W 0000 0010 0000 Configures the locati...

Page 81: ...Address 000D0024 DPWM 0 Sample Trigger 1 Register Figure 2 26 DPWM Sample Trigger 2 Register DPWMSAMPTRIG2 17 6 5 0 SAMPLE_TRIGGER Reserved R W 0000 0010 0000 R 00 0000 LEGEND R W Read Write R Read only n value after reset Table 2 15 DPWM Sample Trigger 2 Register DPWMSAMPTRIG2 Register Field Descriptions Bit Field Type Reset Description 17 6 SAMPLE_ TRIGGER R W 0000 0010 0000 Configures the locat...

Page 82: ...ase Trigger Register Address 000D0028 DPWM 0 Phase Trigger Register Figure 2 27 DPWM Phase Trigger Register DPWMPHASETRIG 17 4 3 0 PHASE_TRIGGER Reserved R W 00 0000 0000 0000 R 0000 LEGEND R W Read Write R Read only n value after reset Table 2 16 DPWM Phase Trigger Register DPWMPHASETRIG Register Field Descriptions Bit Field Type Reset Description 17 4 PHASE_TRIGGER R W 00 0000 0000 0000 Configur...

Page 83: ...cle Adjust A Register Address 000A002C DPWM 1 Cycle Adjust A Register Address 000D002C DPWM 0 Cycle Adjust A Register Figure 2 28 DPWM Cycle Adjust A Register DPWMCYCADJA 15 0 CYCLE_ADJUST_A R W 0000 0000 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 2 17 DPWM Cycle Adjust A Register DPWMCYCADJA Register Field Descriptions Bit Field Type Reset Description 15 0 CYCLE_ADJUST_...

Page 84: ...e Adjust B Register Address 000A0030 DPWM 1 Cycle Adjust B Register Address 000D0030 DPWM 0 Cycle Adjust B Register Figure 2 29 DPWM Cycle Adjust B Register DPWMCYCADJB 15 0 CYCLE_ADJUST_B R W 0000 0000 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 2 18 DPWM Cycle Adjust B Register DPWMCYCADJB Register Field Descriptions Bit Field Type Reset Description 15 0 CYCLE_ADJUST_ B...

Page 85: ...sonant Duty Register Address 000A0034 DPWM 1 Resonant Duty Register Address 000D0034 DPWM 0 Resonant Duty Register Figure 2 30 DPWM Resonant Duty Register DPWMRESDUTY 15 0 RESONANT_DUTY R W 0000 0000 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 2 19 DPWM Resonant Duty Register DPWMRESDUTY Register Field Descriptions Bit Field Type Reset Description 15 0 RESONANT _DUTY R W ...

Page 86: ... Fault Module enable 0 All DPWM Fault Modules disabled Default 1 All DPWM Fault Modules enabled 30 CBC_FAULT_EN R W 0 Cycle by cycle Fault Enable 0 Cycle by cycle just shortens DPWM pulses 1 Consecutive cycle by cycle events beyond CBC_MAX_COUNT will cause the DPWM to shut off as with any other fault 29 Reserved R 0 28 24 CBC_MAX _COUNT R W 0 0000 Cycle by Cycle Fault Count sets the number of rece...

Page 87: ...it Field Type Reset Description 7 PWM_B_CHECK R 0 Value of PWM B internal check 0 Passed checks 1 Failed checks override required to enable output 6 PWM_A_CHECK R 0 Value of PWM B input 0 Passed check 1 Failed check override required to enable output 5 GPIO_B_IN R 0 Value of PWM B input 0 Low signal on PWM B 1 High signal on PWM B 4 GPIO_A_IN R 0 Value of PWM A input 0 Low signal on PWM A 1 High v...

Page 88: ... PRD_INT_SCALE R W 0 R W 0 R W 0 R W 0 R W 1111 LEGEND R W Read Write R Read only n value after reset Table 2 22 DPWM Interrupt Register DPWMINT Register Field Descriptions Bit Field Type Reset Description 22 MODE_SWITCH R 0 Mode Switching Flag 0 Flag is not asserted 1 Flag is set 21 FLT_A R 0 Fault A Flag 0 Flag is not asserted 1 Flag is set 20 FLT_B R 0 Fault B Flag 0 Flag is not asserted 1 Flag...

Page 89: ...Enables generation of periodic PWM interrupt 3 0 PRD_INT_SCALE R W 1111 This value scales the period interrupt signal from an interrupt every switching cycle to 16 switching cycles 0000 Period Interrupt generated every switching cycle Default 0001 Period Interrupt generated once every 2 switching cycles 0010 Period Interrupt generated once every 4 switching cycles 0011 Period Interrupt generated o...

Page 90: ...1 Counter Preset Register Address 000D0044 DPWM 0 Counter Preset Register Figure 2 34 DPWM Counter Preset Register DPWMCNTPRE 17 4 3 0 PRESET Reserved R W 00 0000 0000 0000 R 0000 LEGEND R W Read Write R Read only n value after reset Table 2 23 DPWM Counter Preset Register DPWMCNTPRE Register Field Descriptions Bit Field Type Reset Description 17 4 PRESET R W 00 0000 0000 0000 Counter preset value...

Page 91: ...dress 000A0048 DPWM 1 Blanking A Begin Register Address 000D0048 DPWM 0 Blanking A Begin Register Figure 2 35 DPWM Blanking A Begin Register DPWMBLKABEG 17 4 3 0 BLANK_A_BEGIN Reserved R W 00 0000 0000 0000 R 0000 LEGEND R W Read Write R Read only n value after reset Table 2 24 DPWM Blanking A Begin Register DPWMBLKABEG Register Field Descriptions Bit Field Type Reset Description 17 4 BLANK_A_BEGI...

Page 92: ...r Address 000A004C DPWM 1 Blanking A End Register Address 000D004C DPWM 0 Blanking A End Register Figure 2 36 DPWM Blanking A End Register DPWMBLKAEND 17 4 3 0 BLANK_A_END Reserved R W 00 0000 0000 0000 R 0000 LEGEND R W Read Write R Read only n value after reset Table 2 25 DPWM Blanking A End Register DPWMBLKAEND Register Field Descriptions Bit Field Type Reset Description 17 4 BLANK_A_END R W 00...

Page 93: ...dress 000A0050 DPWM 1 Blanking B Begin Register Address 000D0050 DPWM 0 Blanking B Begin Register Figure 2 37 DPWM Blanking B Begin Register DPWMBLKBBEG 17 4 3 0 BLANK_B_BEGIN Reserved R W 00 0000 0000 0000 R 0000 LEGEND R W Read Write R Read only n value after reset Table 2 26 DPWM Blanking B Begin Register DPWMBLKBBEG Register Field Descriptions Bit Field Type Reset Description 17 4 BLANK_B_BEGI...

Page 94: ...r Address 000A0054 DPWM 1 Blanking B End Register Address 000D0054 DPWM 0 Blanking B End Register Figure 2 38 DPWM Blanking B End Register DPWMBLKBEND 17 4 3 0 BLANK_B_END Reserved R W 00 0000 0000 0000 R 0000 LEGEND R W Read Write R Read only n value after reset Table 2 27 DPWM Blanking B End Register DPWMBLKBEND Register Field Descriptions Bit Field Type Reset Description 17 4 BLANK_B_END R W 00...

Page 95: ...s 000A0058 DPWM 1 Minimum Duty Cycle High Register Address 000D0058 DPWM 0 Minimum Duty Cycle High Register Figure 2 39 DPWM Minimum Duty Cycle High Register DPWMMINDUTYHI 17 4 3 0 MIN_DUTY_HIGH Reserved R W 00 0000 0000 0000 R 0000 LEGEND R W Read Write R Read only n value after reset Table 2 28 DPWM Minimum Duty Cycle High Register DPWMMINDUTYHI Register Field Descriptions Bit Field Type Reset D...

Page 96: ...ess 000A005C DPWM 1 Minimum Duty Cycle Low Register Address 000D005C DPWM 0 Minimum Duty Cycle Low Register Figure 2 40 DPWM Minimum Duty Cycle Low Register DPWMMINDUTYLO 17 4 3 0 MIN_DUTY_LOW Reserved R W 00 0000 0000 0000 R 0000 LEGEND R W Read Write R Read only n value after reset Table 2 29 DPWM Minimum Duty Cycle Low Register DPWMMINDUTYLO Register Field Descriptions Bit Field Type Reset Desc...

Page 97: ...le Register Address 00070060 DPWM 2 Adaptive Sample Register Address 000A0060 DPWM 1 Adaptive Sample Register Address 000D0060 DPWM 0 Adaptive Sample Register Figure 2 41 DPWM Adaptive Sample Register DPWMADAPTIVE 11 0 ADAPT_SAMP R W 0000 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 2 30 DPWM Adaptive Sample Register DPWMADAPTIVE Register Field Descriptions Bit Field Type ...

Page 98: ...te R Read only n value after reset Table 2 31 DPWM Fault Status DPWMFLTSTAT Register Field Descriptions Bit Field Type Reset Description 5 BURST R 0 Burst Mode Detection Status 0 Burst Mode Detection is not asserted 1 Burst Mode Detection is set 4 IDE_DETECT R 0 IDE Detection Status from Analog Comparators 0 IDE Detection is not asserted 1 IDE Detection is set 3 FLT_A R 0 Fault A Detection Statu 0...

Page 99: ...0068 DPWM 0 Auto Switch High Upper Thresh Register Figure 2 43 DPWM Auto Switch High Upper Thresh Register DPWMAUTOSWHIUPTHRESH 17 4 3 0 AUTO_SWITCH_HIGH_UPPER Reserved R W 00 0000 0000 0000 R 0000 LEGEND R W Read Write R Read only n value after reset Table 2 32 DPWM Auto Switch High Upper Thresh Register DPWMAUTOSWHIUPTHRESH Register Field Descriptions Bit Field Type Reset Description 17 4 AUTO_S...

Page 100: ...006C DPWM 0 Auto Switch High Lower Thresh Register Figure 2 44 DPWM Auto Switch High Lower Thresh Register DPWMAUTOSWHILOWTHRESH 17 4 3 0 AUTO_SWITCH_HIGH_LOWER Reserved R W 00 0000 0000 0000 R 0000 LEGEND R W Read Write R Read only n value after reset Table 2 33 DPWM Auto Switch High Lower Thresh Register DPWMAUTOSWHILOWTHRESH Register Field Descriptions Bit Field Type Reset Description 17 4 AUTO...

Page 101: ...00D0070 DPWM 0 Auto Switch Low Upper Thresh Register Figure 2 45 DPWM Auto Switch Low Upper Thresh Register DPWMAUTOSWLOUPTHRESH 17 4 3 0 AUTO_SWITCH_LOW_UPPER Reserved R W 00 0000 0000 0000 R 0000 LEGEND R W Read Write R Read only n value after reset Table 2 34 DPWM Auto Switch Low Upper Thresh Register DPWMAUTOSWLOUPTHRESH Register Field Descriptions Bit Field Type Reset Description 17 4 AUTO_SW...

Page 102: ...0D0074 DPWM 0 Auto Switch Low Lower Thresh Register Figure 2 46 DPWM Auto Switch Low Lower Thresh Register DPWMAUTOSWLOLOWTHRESH 17 4 3 0 AUTO_SWITCH_LOW_LOWER Reserved R W 00 0000 0000 0000 R 0000 LEGEND R W Read Write R Read only n value after reset Table 2 35 DPWM Auto Switch Low Lower Thresh Register DPWMAUTOSWLOLOWTHRESH Register Field Descriptions Bit Field Type Reset Description 17 4 AUTO_S...

Page 103: ...0 0 7 6 4 3 2 1 0 Reserved PWM_MODE Reserved CLA_EN Reserved R 0000 0 R W 00 R 00 R W 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 2 36 DPWM Auto Config Max Register DPWMAUTOMAX Register Field Descriptions Bit Field Type Reset Description 31 28 PWM_B_INTRA _MUX R W 000 Interchanges DPWM signals post edge generation 0 Pass through Default 1 Edge gen output this module 2 PWM C t...

Page 104: ... disabled Default 1 CBC enabled Multi and Resonant Modes 0 PWM A and PWM B operate independently Default 1 PWM A and PWM B pulse matching enabled 18 17 Reserved R 00 16 MASTER_SYNC _CNTL_SEL R W 0 Configures master sync location 0 Master Sync controlled by Phase Trigger Register Default 1 Master Sync controlled by CLA value 15 14 Reserved R 00 13 CBC_SYNC_CUR _LIMIT_EN R W 0 Sets how current limit...

Page 105: ... 0 7 6 4 3 2 1 0 Reserved PWM_MODE Reserved CLA_EN Reserved R 0000 0 R W 000 R 00 R W 1 R 0 LEGEND R W Read Write R Read only n value after reset Table 2 37 DPWM Auto Config Mid Register DPWMAUTOMID Register Field Descriptions Bit Field Type Reset Description 31 28 PWM_B_INTRA _MUX R W 000 Interchanges DPWM signals post edge generation 0 Pass through Default 1 Edge gen output this module 2 PWM C t...

Page 106: ...0 CBC disabled Default 1 CBC enabled Multi and Resonant Modes 0 PWM A and PWM B operate independently Default 1 PWM A and PWM B pulse matching enabled 18 17 Reserved R 00 16 MASTER_SYNC _CNTL_SEL R W 0 Configures master sync location 0 Master Sync controlled by Phase Trigger Register Default 1 Master Sync controlled by CLA value 15 14 Reserved R 00 13 CBC_SYNC_CUR _LIMIT_EN R W 0 Sets how current ...

Page 107: ... Field Descriptions Bit Field Type Reset Description 16 EDGE_EN R W 0 Enables edge generate module When combining dpwm s all modules must have this bit enabled 15 Reserved R 0 14 12 A_ON_EDGE R W 000 Select input edge to trigger A ON output edge 0 Current DPWM posedge A 1 Current DPWM negedge A 2 Current DPWM posedge B 3 Current DPWM negedge B 4 Below n 1 DPWM posedge A 5 Below n 1 DPWM negedge A ...

Page 108: ... 38 DPWM Edge PWM Generation Control Register DPWMEDGEGEN Register Field Descriptions continued Bit Field Type Reset Description 2 0 B_OFF_EDGE R W 11 Select input edge to trigger B OFF output edge 0 Current DPWM posedge A 1 Current DPWM negedge A 2 Current DPWM posedge B 3 Current DPWM negedge B 4 Below n 1 DPWM posedge A 5 Below n 1 DPWM negedge A 6 Below n 1 DPWM posedge B 7 Below n 1 DPWM nege...

Page 109: ...uty Read Register Address 00070084 DPWM 2 Filter Duty Read Register Address 000A0084 DPWM 1 Filter Duty Read Register Address 000D0084 DPWM 0 Filter Duty Read Register Figure 2 50 DPWM Filter Duty Read Register DPWMFILTERDUTYREAD 17 0 FILTER_DUTY R 0 LEGEND R W Read Write R Read only n value after reset Table 2 39 DPWM Filter Duty Read Register DPWMFILTERDUTYREAD Register Field Descriptions Bit Fi...

Page 110: ...088 DPWM 3 BIST Status Register Address 00070088 DPWM 2 BIST Status Register Address 000A0088 DPWM 1 BIST Status Register Address 000D0088 DPWM 0 BIST Status Register Figure 2 51 DPWM BIST Status Register DPWMBISTSTAT 14 0 BIST_CNT R 0 LEGEND R W Read Write R Read only n value after reset Table 2 40 DPWM BIST Status Register DPWMBISTSTAT Register Field Descriptions Bit Field Type Reset Description...

Page 111: ...fier The other input to this differential amplifier comes from a Digital to Analog Converter DAC which has an effective range of 0 to 1 6V This DAC output typically represents a target for a regulated value reference There is a gain programmable differential amplifier which outputs the difference between the DAC output and the Front End input This analog signal typically represents the error betwe...

Page 112: ...Current Mode control Front End 2 is recommended for Peak Current mode control because blanking time is available only on FE2 in UCD3138 RMH RHA RGC All of these are described in more details in later sections of this chapter Topic Page 3 1 Error ADC and Front End Gain 113 3 2 Front End DAC 118 3 3 Ramp Module 119 3 4 Successive Approximation Mode 123 3 5 Absolute Value Without SAR 124 3 6 EADC Mod...

Page 113: ...e gain is increased if the EADC output is less than 1 4 of its range at the current gain By setting the AUTO_GAIN_SHIFT_MODE bit in the EADCCTRL register the second auto gain mode can be enabled In this mode the shift points are set by the Filter nonlinear mode thresholds These thresholds are described in Section 4 5 There are 3 Filters with non linear thresholds The FECTRLxMUX register in Chapter...

Page 114: ... Gain www ti com 114 SNIU028A February 2016 Revised April 2016 Submit Documentation Feedback Copyright 2016 Texas Instruments Incorporated Front End Here is a graphical representation of the EADC output Figure 3 2 The EADC error output as described above can be read from the EADC raw value register eadc_error FeCtrl0Regs EADCRAWVALUE bit RAW_ERROR_VALUE It is also sent to the Filter and is one of ...

Page 115: ... Sample triggers can also be divided so that the EADC only fires every 1 to 16 sample triggers FeCtrl0Regs EADCCTRL bit SAMP_TRIG_SCALE 4 trigger every 5 sample triggers 3 1 4 EADC Timing The EADC takes either 16 or 32 cycles of the 250 MHz high speed clock to complete an analog to digital conversion The timing logic runs continuously producing samples every 64 or 128 ns This gives maximum sample ...

Page 116: ...number of samples immediately after the sample trigger at the EADC sample rate of 16 or 8 MHz It then triggers the Filter and provides the average of the samples as the filter input Figure 3 3 Consecutive Mode of Averaging by EADC Spatial mode takes one sample for each sample trigger and sends averaged data to the filter after the specified number of sample triggers Figure 3 4 Spatial Mode of Aver...

Page 117: ...t End can be used without enabling the EADC There is also a bit in the Loop Mux which must be set for the Front End 0 to start LoopMuxRegs GLBEN bit FE_CTRL0_EN 1 0 is default The GLBEN register is a special register with enables for all front ends and all DPWMs in the same register It is designed to allow simultaneous start up of all front ends and DPWMs by writing to the whole register at once T...

Page 118: ... 3 5 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DAC Value Dither This dither has a 4 bit counter driven by a selected DWPM signal which will switch back and forth between 2 DAC values For example if the DAC value is set to 100 75 16 there will be a 0b11000100 equivalent to 100 in the 10 DAC bits and a 0b1100 equivalent to 12 or 0 75 x 16 in the 4 dither bits The dither logic will put out a 100 for 4 counts a...

Page 119: ...ramp down of current and voltage It is also used to ramp up and down the pulse width of Synchronous Rectifier FET pulses to avoid glitches when enabling and disabling synchronous rectification Portions of the Ramp Module are also used for Prebias handling The Ramp module is also used for the ramp compensation in peak current mode The Ramp module can be used for only one purpose at a time There are...

Page 120: ...t has 7 bits so the register can hold values from 0 to 127 corresponding to 1 to 128 cycles The Switch Cycle signal is a DPWM output The DPWM output used for the Ramp module is the same as the one for dither above LoopMuxRegs FECTRL2MUX bit DPWM3_B_TRIG_EN 1 set DPWM3B up to trigger dither and ramp modules The step size is an unsigned value The Ramp module logic checks the start and end values If ...

Page 121: ...e DACSATSTEP value The increment will continue until the EADC is out of saturation This increment when the EADC is in saturation occurs periodically when the DAC would be updated with a new DAC value during the ramp If the step value is carefully chosen this mode may help to keep the EADC from saturating during a ramp up It may however make the ramp timing undeterministic and non monotonic 3 3 7 U...

Page 122: ... The fractional position of the step size register is the same which means that bit 10 in the step size register represents a 4 nanosecond step All the same start criteria can be used for the Sync FET Ramp The difference is that the SYNC_FET_EN bit is set in the RAMPCTRL register instead of the RAMP_EN bit The Sync FET ramp only works in normal mode It cannot be used with Cycle By Cycle CBC curren...

Page 123: ...firmware Initially the MSB of the 10 bit DAC value is set to 1 or the DAC setpoint is placed at the midpoint of its range An EADC sample is captured and compared Based on the polarity and magnitude of the EADC error the AFE gain and DAC setpoint are adjusted 3 4 3 Non Continuous SAR Mode UCD3138 features two modes when it attempts to use a SAR algorithm to determine an absolute voltage The first m...

Page 124: ... Constant Current Control 2 Mode CPCC module controls switching between Standard mode and Continuous SAR Mode 3 7 Front End Control Registers Registers for Front End Control modules 0 2 are identical in their bit definitions 3 7 1 Ramp Control Register RAMPCTRL Address 0x0008_0000 Front End Control 2 Ramp Control Register Address 0x000B_0000 Front End Control 1 Ramp Control Register Address 0x000E...

Page 125: ...ART_SEL R W 0 Peak Current Mode Ramp Start Value Select 0 Ramp starts from value programmed in DAC_VALUE bits in EADC_DAC_VALUE Register Default 1 Ramp starts from filter output selected by PCM_FILTER_SEL bits in Loop Mux register PCMCTRL 7 SYNC_FET_EN R W 0 Enables SyncFET Ramp Operation 0 SyncFET Ramp Operation disabled Default 1 SyncFET Ramp Operation enabled 6 5 MASTER_SEL R W 00 Selects Maste...

Page 126: ...us 0 No Ramp Delay Complete has been declared 1 Ramp Delay Complete has been declared 9 RAMP_DLY_INT _STATUS R 0 Ramp Delay Complete latched status 0 No Ramp Delay Complete has been declared 1 Ramp Delay Complete has been declared 8 PREBIAS_INT _STATUS R 0 Pre Bias Complete latched status 0 No Pre Bias Complete has been declared 1 Pre Bias Complete has been declared 7 EADC_SAT_HIGH R 0 EADC Satura...

Page 127: ... RAMPCYCLE Register Field Descriptions Bit Field Type Reset Description 23 8 DELAY_CYCLES R W 0000 0000 0000 0000 Configures the number of delay cycles before an initiation of ramp sequence Each delay cycle consists of n switching cycles as specified by SWITCH_CYC_PER_STEP Bits 6 0 Number of delay cycles can vary from 0 to 65535 0 Ramp starts without delay Default 1 Ramp starts after 1 SWITCH_CYC_...

Page 128: ...s 0x000E_000C Front End Control 0 EADC DAC Value Register Figure 3 12 EADC DAC Value Register EADCDAC 15 14 13 0 DAC_DITHER_EN Reserved DAC_VALUE R W 0 R 0 R W 00 1111 1111 0000 LEGEND R W Read Write R Read only n value after reset Table 3 6 EADC DAC Value Register EADCDAC Register Field Descriptions Bit Field Type Reset Description 15 DAC_DITHER_EN R W 0 DAC Dithering Enable 0 DAC Dithering disab...

Page 129: ...ess 0x000B_0010 Front End Control 1 Ramp DAC Ending Register Address 0x000E_0010 Front End Control 0 Ramp DAC Ending Register Figure 3 13 Ramp DAC Ending Value Register RAMPDACEND 13 0 RAMP_DAC_VALUE R W 00 0000 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 3 7 Ramp DAC Ending Value Register RAMPDACEND Register Field Descriptions Bit Field Type Reset Description 13 0 RAMP_D...

Page 130: ...ess 0x000E_0014 Front End Control 0 DAC Step Register Figure 3 14 DAC Step Register DACSTEP 17 0 DAC_STEP R W 00 0000 0000 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 3 8 DAC Step Register DACSTEP Register Field Descriptions Bit Field Type Reset Description 17 0 DAC_STEP R W 00 0000 0000 0000 0000 Programmable 18 bit unsigned DAC Step Bits 17 10 represent the real portion...

Page 131: ... Control 0 DAC Saturation Step Register Figure 3 15 DAC Saturation Step Register DACSATSTEP 13 0 DAC_SAT_STEP R W 00 0000 0000 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 3 9 DAC Saturation Step Register DACSATSTEP Register Field Descriptions Bit Field Type Reset Description 13 0 DAC_SAT_STEP R W 00 0000 0000 0000 Programmable DAC Saturation Step LSB equals 0 009765625mV ...

Page 132: ... 00 R W 01 1000 R 00 R W 01 1000 LEGEND R W Read Write R Read only n value after reset Table 3 10 EADC Trim Register EADCTRIM Register Field Descriptions Bit Field Type Reset Description 29 24 GAIN3_TRIM R W 01 1000 Sets trim for 8X AFE Gain Register will be programmed during test and should not be overwritten by firmware 23 22 Reserved R 00 21 16 GAIN2_TRIM R W 01 1000 Sets trim for 4X AFE Gain R...

Page 133: ... Front End Ramp Comparator enabled 27 EN_HYST_HIGH R W 0 Increase comparator trip point by 70mV 0 Disables increase of ramp comparator trip point Default 1 Enables increase of ramp comparator trip point 26 EN_HYST_LOW R W 0 Decrease comparator trip point by 70mV 0 Disables decrease of ramp comparator trip point Default 1 Enables decrease of ramp comparator trip point 25 22 SAMP_TRIG _SCALE R W 000...

Page 134: ...d sample trigger from DPWM modules Default 1 EADC samples averaged based on received sample triggers from DPWM modules 2 sample triggers required for a single averaged sample to filter 4 sample triggers required for a single averaged sample to filter module 10 9 AVG_MODE_SEL R W 00 Averaging Mode Configuration 0 2x Averaging Default 1 4x Averaging 2 8x Averaging 8 6 EADC_MODE R W 000 Selects EADC ...

Page 135: ...TRIM R W 000000 EADC Reference Trim Value Bits will be programmed during test and should not be overwritten by firmware 9 EADC_REF _RESET R W 1 EADC Reference Reset 0 Reference not in reset 1 Resets Reference Default 8 EADC_REF_EN R W 0 EADC Reference Enable 0 Disables EADC Reference Default 1 Enables EADC Reference 7 5 Reserved R 000 4 EADC_GAIN_CAL R W 0 EADC Gain Calibration Mode Enable 0 Disab...

Page 136: ...PRE_BIAS_POL R W 0 Configures polarity of received error voltage 0 Error equals Vref Vin Default 1 Error equals Vin Vref 16 PRE_BIAS_EN R W 0 Enable Pre Biasing of Error ADC Ramp should be disabled during pre biasing bit 0 of Ramp Control Register 0 Pre Biasing has not been initiated Default 1 Pre Biasing by hardware has been enabled 15 8 PRE_BIAS _RANGE R W 1111 1111 Sets the acceptable range aro...

Page 137: ...23 16 15 14 SAMPLES_PER_ADJ Reserved R W 0000 0000 R 00 13 0 MAX_DAC_ADJ R W 00 0000 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 3 14 Pre Bias Control Register 1 PREBIASCTRL1 Register Field Descriptions Bit Field Type Reset Description 23 16 SAMPLES_PER _ADJ R W 0000 0000 Configures the number of EADC samples between Pre Bias DAC setpoint adjustments 0 DAC Setpoint adjust...

Page 138: ...TION R 0000 00 R W 00 LEGEND R W Read Write R Read only n value after reset Table 3 15 SAR Control Register SARCTRL Register Field Descriptions Bit Field Type Reset Description 31 24 EADC_WINDOW _2 R W 0010 1000 Configures acceptable range of error values to transition to AFE Gain of 2 during SAR process 23 16 EADC_WINDOW _1 R W 0110 0000 Configures acceptable range of error values to transition t...

Page 139: ...ng Register SARTIMING 10 8 SAR_TIMING_UPPER R W 100 7 6 5 4 3 2 1 0 Reserved SAR_TIMING_MID Reserved SAR_TIMING_LOWER R 0 R W 011 R 0 R W 010 LEGEND R W Read Write R Read only n value after reset Table 3 16 SAR Timing Register SARTIMING Register Field Descriptions Bit Field Type Reset Description 10 8 SAR_TIMING _UPPER R W 100 Configures timing for Bits 9 8 of DAC setpoint for SAR Algorithm 7 Rese...

Page 140: ...E R 0 R 0 R 0 R 0 7 0 ERROR_VALUE R 0 LEGEND R W Read Write R Read only n value after reset Table 3 17 EADC Value Register EADCVALUE Register Field Descriptions Bit Field Type Reset Description 25 16 ABS_VALUE R 0 10 bit Absolute Value calculated by Front End Control Module with a resolution of 1 5625mV bit 15 EADC_SAT_HIGH R 0 EADC Saturation High Indicator 0 EADC output is not saturated at high ...

Page 141: ... Front End Control 1 EADC Raw Value Register Address 0x000E_003C Front End Control 0 EADC Raw Value Register Figure 3 24 EADC Raw Value Register EADCRAWVALUE 8 0 RAW_ERROR_VALUE R 0 LEGEND R W Read Write R Read only n value after reset Table 3 18 EADC Raw Value Register EADCRAWVALUE Register Field Descriptions Bit Field Type Reset Description 8 0 RAW_ERROR _VALUE R 0 Signed 9 bit Error value measu...

Page 142: ...d Control 2 DAC Status Register Address 0x000B_0040 Front End Control 1 DAC Status Register Address 0x000E_0040 Front End Control 0 DAC Status Register Figure 3 25 DAC Status Register DACSTAT 9 0 DAC_VALUE R 00 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 3 19 DAC Status Register DACSTAT Register Field Descriptions Bit Field Type Reset Description 9 0 DAC_VALUE R 00 0000 0...

Page 143: ...lculations Programmable clamps on Integrator Branch and Filter Output Ability to load values into internal filter registers while system is running Ability to stall calculations on any of the individual filter branches Ability to clear and stall calculations on any of the individual filter branches Duty Cycle Resonant Period or phase shift generation based on filter output Flux Balancing Voltage f...

Page 144: ... to round to a decreased resolution immediately The filter is relatively complex so scaling is discussed in sections After the filter math details are described the registers which control the filter are documented 4 1 1 Filter Input and Branch Calculations Here is a block diagram of the first part of the filter with bit width information Figure 4 1 All values shown in the filter are signed number...

Page 145: ...ed by the Ki coefficient Note that the trapezoidal mode will normally have double the output of the simple Xn value This will change the overall gain of the I stage by a factor of two This must be taken into account if the Xn addition mode is changed The output of this multiplication will always fit within 24 bits This value is then added to the existing I value The hardware will automatically cla...

Page 146: ... for 24 bits the output of the saturation logic will be set to the maximum 0x7fffff or 8388607 Negative values out of range will be clamped to the most negative value The output of the saturation section goes to a programmable shifter which can be programmed for 8 different shifts including no shift at all This can be used to compensate for the scaling of the filter coefficients After the scaling ...

Page 147: ... PID output is multiplied by one of several 14 bit unsigned numbers giving a 38 bit output For the Filter Duty calculation there are 4 numbers which can be used See Section 4 3 8 for a discussion of these numbers For the Filter Period calculation only 2 numbers can be selected After the multiplication there is a 38 bit signed result Negative values are clamped to zero and the sign bit is removed T...

Page 148: ...50 duty cycle 4 2 Filter Status Register The Filter status register has 5 bits FILTER_BUSY YN_LOW_CLAMP YN_HIGH_CLAMP KI_YN_LOW_CLAMP KI_YN_HIGH_CLAMP The FILTER_BUSY bit is high when the filter is calculating This calculation time is very short only a few instruction cycles It is very difficult to reliably detect the high time of the Filter Busy bit The other bits are written to each time the fil...

Page 149: ...4 Kp Off Kd Off Ki Off The KP_OFF KD_OFF and KI_OFF bits disable these sections of the filter and replace those values with a zero They also clear any history to a zero where it is present I and D Note that the history values are loaded with a zero the next time the filter is triggered Normally the EADC is triggered by a sample trigger signal from a DPWM module When the EADC conversion is complete...

Page 150: ...from the DPWM Period register and this is used for most topologies However there are two other DPWM registers which can also be sent to the Filter for this value See 2 17 3 Filter Duty Select for more details 4 3 9 Switching Period as Output Multiplier Using the Switching Period as an output multiplier leads to the DPWM duty being directly proportional to the Filter output with a full range output...

Page 151: ... output at 50 which should reduce the size of any limit cycling 4 3 11 Feed Forward as Output Multiplier When the feed forward is selected as the output multiplier the multiplier value is the most significant 14 bits of the filter output from a different filter The FILTERMUX register in the Loop Mux is also used to select this filter Configuring the link between the two filters is simple and is sh...

Page 152: ... register is used in the CPU Sample mode described above This is where the firmware writes the CPU controlled value in CPU Sample mode See Section 4 3 2 4 4 2 Filter XN Read Register This register provides both Xn and Xn 1 for read by the firmware 4 4 3 Filter YN Read Registers There are three read registers for internal filter results FILTERKIYNREAD FILTERKDYNREAD FILTERYNREAD These provide the o...

Page 153: ... COECONFIG register is used to configure filter coefficients for nonlinear mode Each Filter coefficient has from 2 to 4 values which are programmable via Filter registers Kp Ki and Kd are arranged into 7 coefficient sets as shown in Figure 4 4 Figure 4 4 These sets are designed so that bandwidth increases as the set goes from A to G These sets can be mapped in any possible combination into 7 bins ...

Page 154: ...ust be increasing with limit 0 the lowest possible value Limit 1 higher and so on In symmetric mode all limit values must be positive Each bin has a separate bit which selects one of the 2 alpha values Here is a code example which uses all the Coefficient sets with increasing bandwidth for increasing error Filter0Regs COEFCONFIG bit BIN0_CONFIG 0 coefficient set A Filter0Regs COEFCONFIG bit BIN1_C...

Page 155: ...EF_0 500 Filter1Regs FILTERKICOEF0 bit KI_COEF_0 150 Filter1Regs FILTERKDCOEF0 bit KD_COEF_0 250 4 7 Alpha Registers The FILTERKDALPHA register holds the two alpha coefficients which can be selected by the BINx_ALPHA bits in the COEFCONFIG register Alpha is stored as a 9 bit signed number Here is an example which only loads KD_ALPHA_0 Filter1Regs FILTERKDALPHA bit KD_ALPHA_0 134 4 8 Filter Nonline...

Page 156: ... the Filter is calculating when the Filter Preset is enabled the target register in the Filter is not written to immediately The hardware waits for the filter to stop calculating and then writes to the target register If the filter is not running the Filter Preset takes effect immediately There are three bit fields in the Filter Preset Register The PRESET_EN bit is set to enable the preset and can...

Page 157: ...aiting for new data 1 Filter busy calculating 3 YN_LOW_CLAMP R 0 PID Output Low Rail Indicator 0 PID Output not equal to low rail 1 PID Output equal to low rail 2 YN_HIGH_ CLAMP R 0 PID Output High Rail Indicator 0 PID Output not equal to high rail 1 PID Output equal to high rail 1 KI_YN_LOW_ CLAMP R 0 KI Feedback Low Rail Indicator 0 KI Feedback not equal to low rail 1 KI Feedback equal to low ra...

Page 158: ...dule Default 1 KComp received from Loop Mux module 13 12 OUTPUT_MULT _SEL R W 00 Selects output multiplicand used for multiplying with filter output to calculate DPWM Duty value 0 KComp received from Loop Mux module Default 1 Switching period received from Loop Mux module 2 Feed Forward value received from Loop Mux module 3 Resonant Duty value received from DPWM Module 11 9 YN_SCALE R W 000 Contro...

Page 159: ...h KD_YN cleared to zero 0 KD branch calculating new outputs Default 1 KD branch turned off 3 KI_OFF R W 0 Turns off the KI branch KI_YN cleared to zero 0 KI branch calculating new outputs Default 1 KI branch halted 2 FORCE_START R W 0 Initiates a filter calculation under firmware control 0 No calculation started Default 1 Calculation started 1 USE_CPU _SAMPLE R W 0 Forces filter to use error sampl...

Page 160: ...090008 Filter 1 CPU XN Register Address 000C0008 Filter 0 CPU XN Register Figure 4 8 CPU XN Register CPUXN 8 0 CPU_SAMPLE R W 0 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 4 3 CPU XN Register CPUXN Register Field Descriptions Bit Field Type Reset Description 8 0 CPU_SAMPLE R W 0 0000 0000 Forced Xn value allows processor to use filter as ALU Set Bit 2 of Filter Control Re...

Page 161: ...0C Filter 1 XN Read Register Address 000C000C Filter 0 XN Read Register Figure 4 9 Filter XN Read Register FILTERXNREAD 24 16 15 9 8 0 XN_M1 Reserved XN R 0 R 000 0000 R 0 LEGEND R W Read Write R Read only n value after reset Table 4 4 Filter XN Read Register FILTERXNREAD Register Field Descriptions Bit Field Type Reset Description 24 16 XN_M1 R 0 9 bit signed XN_M1 register value read only 15 9 R...

Page 162: ...00060010 Filter 2 KI_YN Read Register Address 00090010 Filter 1 KI_YN Read Register Address 000C0010 Filter 0 KI_YN Read Register Figure 4 10 Filter KI_YN Read Register FILTERKIYNREAD 23 0 KI_YN R 0 LEGEND R W Read Write R Read only n value after reset Table 4 5 Filter KI_YN Read Register FILTERKIYNREAD Register Field Descriptions Bit Field Type Reset Description 23 0 KI_YN R 0 24 bit signed KI_YN...

Page 163: ...Address 00060014 Filter 2 KD_YN Register Address 00090014 Filter 1 KD_YN Register Address 000C0014 Filter 0 KD_YN Register Figure 4 11 Filter KD_YN Read Register FILTERKDYNREAD 23 0 KD_YN R 0 LEGEND R W Read Write R Read only n value after reset Table 4 6 Filter KD_YN Read Register FILTERKDYNREAD Register Field Descriptions Bit Field Type Reset Description 23 0 KD_YN R 0 24 bit signed KD_YN regist...

Page 164: ...s Incorporated Filter 4 11 7 Filter YN Read Register FILTERYNREAD Figure 4 12 Filter YN Read Register FILTERYNREAD 23 0 YN R 0 LEGEND R W Read Write R Read only n value after reset Table 4 7 9 7 Filter YN Read Register FILTERYNREAD Register Field Descriptions Bit Field Type Reset Description 23 0 YN R 0 24 bit signed YN register value read only ...

Page 165: ...ected Default 1 Bank 1 KD Alpha KD_ALPHA_1 selected 26 24 BIN6_CONFIG R W 000 Selects which coefficient set to place in Bin 6 of Non Linear Table These bits are shadowed and updated to filter when filter is not processing an EADC sample 0 Coefficient Set A Selected Default 1 Coefficient Set B Selected 2 Coefficient Set C Selected 3 Coefficient Set D Selected 4 Coefficient Set E Selected 5 Coeffici...

Page 166: ...2_ALPHA R W 0 Selects which alpha value to use in Bin 2 of Non Linear Table These bits are shadowed and updated to filter when filter is not processing an EADC sample 0 Bank 0 KD Alpha KD_ALPHA_0 selected Default 1 Bank 1 KD Alpha KD_ALPHA_1 selected 10 8 BIN2_CONFIG R W 000 Selects which coefficient set to place in Bin 2 of Non Linear Table These bits are shadowed and updated to filter when filte...

Page 167: ...iptions continued Bit Field Type Reset Description 2 0 BIN0_CONFIG R W 000 Selects which coefficient set to place in Bin 1 of Non Linear Table These bits are shadowed and updated to filter when filter is not processing an EADC sample 0 Coefficient Set A Selected Default 1 Coefficient Set B Selected 2 Coefficient Set C Selected 3 Coefficient Set D Selected 4 Coefficient Set E Selected 5 Coefficient...

Page 168: ... Filter KP Coefficient 0 Register FILTERKPCOEF0 31 16 15 0 KP_COEF_1 KP_COEF_0 R W 0000 0000 0000 0000 R W 0100 0010 0011 0100 LEGEND R W Read Write R Read only n value after reset Table 4 9 Filter KP Coefficient 0 Register FILTERKPCOEF0 Register Field Descriptions Bit Field Type Reset Description 31 16 KP_COEF_1 R W 0000 0000 0000 0000 KP Coefficient 1 16 bit signed coefficient configurable to an...

Page 169: ...r 1 KP Coefficient 1 Register Address 000C0024 Filter 0 KP Coefficient 1 Register Figure 4 15 Filter KP Coefficient 1 Register FILTERKPCOEF1 15 0 KP_COEF_2 R W 0000 0000 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 4 10 Filter KP Coefficient 1 Register FILTERKPCOEF1 Register Field Descriptions Bit Field Type Reset Description 15 0 KP_COEF_2 R W 0000 0000 0000 0000 KP Coeff...

Page 170: ... Filter KI Coefficient 0 Register FILTERKICOEF0 31 16 15 0 KI_COEF_1 KI_COEF_0 R W 0000 0000 0000 0000 R W 0010 0100 0001 0010 LEGEND R W Read Write R Read only n value after reset Table 4 11 Filter KI Coefficient 0 Register FILTERKICOEF0 Register Field Descriptions Bit Field Type Reset Description 31 16 KI_COEF_1 R W 0000 0000 0000 0000 KI Coefficient 1 16 bit signed coefficient configurable to a...

Page 171: ... Filter KI Coefficient 1 Register FILTERKICOEF1 31 16 15 0 KI_COEF_3 KI_COEF_2 R W 0000 0000 0000 0000 R W 0000 0000 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 4 12 Filter KI Coefficient 1 Register FILTERKICOEF1 Register Field Descriptions Bit Field Type Reset Description 31 16 KI_COEF_3 R W 0000 0000 0000 0000 KI Coefficient 3 16 bit signed coefficient configurable to a...

Page 172: ... Filter KD Coefficient 0 Register FILTERKDCOEF0 31 16 15 0 KD_COEF_1 KD_COEF_0 R W 0000 0000 0000 0000 R W 1100 0100 0000 0001 LEGEND R W Read Write R Read only n value after reset Table 4 13 Filter KD Coefficient 0 Register FILTERKDCOEF0 Register Field Descriptions Bit Field Type Reset Description 31 16 KD_COEF_1 R W 0000 0000 0000 0000 KD Coefficient 1 16 bit signed coefficient configurable to a...

Page 173: ...r 1 KD Coefficient 1 Register Address 000C0034 Filter 0 KD Coefficient 1 Register Figure 4 19 Filter KD Coefficient 1 Register FILTERKDCOEF1 15 0 KD_COEF_2 R W 0000 0000 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 4 14 Filter KD Coefficient 1 Register FILTERKDCOEF1 Register Field Descriptions Bit Field Type Reset Description 15 0 KD_COEF_2 R W 0000 0000 0000 0000 KD Coeff...

Page 174: ...lter KD Alpha Register FILTERKDALPHA 24 16 15 9 8 0 KD_ALPHA_1 Reserved KD_ALPHA_0 R W 0 0000 0000 R 0 R W 0 0101 0010 LEGEND R W Read Write R Read only n value after reset Table 4 15 Filter KD Alpha Register FILTERKDALPHA Register Field Descriptions Bit Field Type Reset Description 24 16 KD_ALPHA_1 R W 0 0000 0000 Bank 1 KD Alpha 9 bit signed value configurable to any bin using the Coefficient Co...

Page 175: ...Address 000C003C Filter 0 Nonlinear Limit Register 0 Figure 4 21 Filter Nonlinear Limit Register 0 FILTERNL0 24 16 15 9 8 0 LIMIT1 Reserved LIMIT0 R W 0 0000 0000 R 0 R W 0 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 4 16 Filter Nonlinear Limit Register 0 FILTERNL0 Register Field Descriptions Bit Field Type Reset Description 24 16 LIMIT1 R W 0 0000 0000 Configures LIMIT1 ...

Page 176: ...Address 000C0040 Filter 0 Nonlinear Limit Register 1 Figure 4 22 Filter Nonlinear Limit Register 1 FILTERNL1 24 16 15 9 8 0 LIMIT3 Reserved LIMIT2 R W 0 0000 0000 R 0 R W 0 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 4 17 Filter Nonlinear Limit Register 1 FILTERNL1 Register Field Descriptions Bit Field Type Reset Description 24 16 LIMIT3 R W 0 0000 0000 Configures LIMIT3 ...

Page 177: ...Address 000C0044 Filter 0 Nonlinear Limit Register 2 Figure 4 23 Filter Nonlinear Limit Register 2 FILTERNL2 24 16 15 9 8 0 LIMIT5 Reserved LIMIT4 R W 0 0000 0000 R 0 R W 0 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 4 18 Filter Nonlinear Limit Register 2 FILTERNL2 Register Field Descriptions Bit Field Type Reset Description 24 16 LIMIT5 R W 0 0000 0000 Configures LIMIT5 ...

Page 178: ...ister Address 000C0048 Filter 0 KI Feedback Clamp High Register Figure 4 24 Filter KI Feedback Clamp High Register FILTERKICLPHI 23 0 KI_CLAMP_HIGH R W 0111 1111 1111 1111 1111 1111 LEGEND R W Read Write R Read only n value after reset Table 4 19 Filter KI Feedback Clamp High Register FILTERKICLPHI Register Field Descriptions Bit Field Type Reset Description 23 0 KI_CLAMP_HIGH R W 0111 1111 1111 1...

Page 179: ...ster Address 000C004C Filter 0 KI Feedback Clamp Low Register Figure 4 25 Filter KI Feedback Clamp Low Register FILTERKICLPLO 23 0 KI_CLAMP_LOW R W 0000 0000 0000 0000 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 4 20 Filter KI Feedback Clamp Low Register FILTERKICLPLO Register Field Descriptions Bit Field Type Reset Description 23 0 KI_CLAMP_LOW R W 0000 0000 0000 0000 00...

Page 180: ... Register Address 000C0050 Filter 0 YN Clamp High Register Figure 4 26 Filter YN Clamp High Register FILTERYNCLPHI 23 0 YN_CLAMP_HIGH R W 0111 1111 1111 1111 1111 1111 LEGEND R W Read Write R Read only n value after reset Table 4 21 Filter YN Clamp High Register FILTERYNCLPHI Register Field Descriptions Bit Field Type Reset Description 23 0 YN_CLAMP_HIGH R W 0111 1111 1111 1111 1111 1111 Sets the ...

Page 181: ... Register Address 000C0054 Filter 0 YN Clamp Low Register Figure 4 27 Filter YN Clamp Low Register FILTERYNCLPLO 23 0 YN_CLAMP_LOW R W 0000 0000 0000 0000 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 4 22 Filter YN Clamp Low Register FILTERYNCLPLO Register Field Descriptions Bit Field Type Reset Description 23 0 YN_CLAMP_LOW R W 0000 0000 0000 0000 0000 0000 Sets the lower...

Page 182: ...ddress 000C0058 Filter 0 Output Clamp High Register Figure 4 28 Filter Output Clamp High Register FILTEROCLPHI 23 0 OUTPUT_CLAMP_HIGH R W 11 1111 1111 1111 1111 LEGEND R W Read Write R Read only n value after reset Table 4 23 Filter Output Clamp High Register FILTEROCLPHI Register Field Descriptions Bit Field Type Reset Description 23 0 OUTPUT_CLAMP _HIGH R W 11 1111 1111 1111 1111 Sets the upper ...

Page 183: ...ddress 000C005C Filter 0 Output Clamp Low Register Figure 4 29 Filter Output Clamp Low Register FILTEROCLPLO 17 0 OUTPUT_CLAMP_LOW R W 00 0000 0000 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 4 24 Filter Output Clamp Low Register FILTEROCLPLO Register Field Descriptions Bit Field Type Reset Description 17 0 OUTPUT_CLAMP _LOW R W 00 0000 0000 0000 0000 Sets the lower limit...

Page 184: ...0000 15 0 PRESET_VALUE R W 0000 0000 0000 0000 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 4 25 Filter Preset Register FILTERPRESET Register Field Descriptions Bit Field Type Reset Description 27 PRESET_EN R W 00 Set to 1 to initiate write of internal filter register Self cleared by hardware after successful programming 26 24 PRESET_REG_ SEL R W 000 Selects internal filte...

Page 185: ...gister GLBEN enables Front Ends and DPWMs simultaneously PWM Global Period Register PWMGLBPRD permits changing multiple periods simultaneously Sync Control Register SYNCCTRL Configures the SYNC pin In addition it controls several modules which tie multiple parts together and have logic of their own Constant Power Constant Current CPCC Module Cycle Adjustment Module used for balancing current and f...

Page 186: ...TRL 187 5 3 External DAC Control EXTDACCTRL 187 5 4 Filter Mux Register FILTERMUX 188 5 5 Filter KComp Registers FILTERKCOMPx 188 5 6 DPWM Mux Register DPWMMUX 188 5 7 Global Enable Register GLBEN 188 5 8 PWM Global Period Register PWMGLBPRD 189 5 9 Sync Control SYNCCTRL 189 5 10 Light Load Burst Mode 189 5 11 Constant Current Constant Power 189 5 12 Analog Peak Current Mode 190 5 13 Automatic Cyc...

Page 187: ...ttling time For DAC settling time please refer to the UCD3138 device datasheet The FECTRLxMUX registers also permit using the Nonlinear Select registers in the Filter to set the step points for Automatic Gain Shifting in the Front End For exact FECTRLxMUX bit assignments see Section 5 14 1 Front End Control 0 Mux Register FECTRL0MUX 5 2 Sample Trigger Control SAMPTRIGCTRL The SAMPTRIGCTRL register...

Page 188: ... two registers FILTERKCOMPA and FILTERKCOMPB FILTER KCOMPA holds both KCOMP0 and KCOMP1 FILTERKCOMPB holds only KCOMP3 All KComp values are 14 bit unsigned numbers 5 6 DPWM Mux Register DPWMMUX DPWMMUX selects inputs to the DPWM modules It selects Ramp module which controls Synchronous FET ramp Master DPWM which provides sync pulse if DPWM module is a slave Source which controls duty cycle resonan...

Page 189: ...can output the Sync pulse from any DPWM or it can be used as a general purpose output It can also output some internal processor clocks for debugging purposes As an input it can be used as a sync input to the DPWMs and as a general purpose input To use it as a sync input to the DPWMs set the EXT_SYNC_EN bit in DPWMCTRL1 5 10 Light Load Burst Mode There are several registers in the Loop Mux related...

Page 190: ...ontrol implementation with UCD3138 5 13 Automatic Cycle Adjustment The Loop Mux contains registers which control and monitor automatic cycle adjustment It can be used to balance current between two legs of a parallel topology such as a multiphase PFC It can also be used for flux balancing in bridge topologies Figure 5 1 illustrates an example of it being used in a bridge topology The cycle adjustm...

Page 191: ..._ADJ_GAIN is 0 the cycle adjustment will be 4 nanoseconds This will make the duty cycle on any DPWM with CLA_DUTY_ADJ_EN set 4 nanoseconds longer 5 14 Loop Mux Registers Reference 5 14 1 Front End Control 0 Mux Register FECTRL0MUX Address 00020000 Figure 5 2 Front End Control 0 Mux Register FECTRL0MUX 13 12 11 10 9 8 NL_SEL DPWM3_FRAME_ SYNC_EN DPWM2_FRAME_ SYNC_EN DPWM1_FRAME_ SYNC_EN DPWM0_FRAME...

Page 192: ...t 1 DPWM 2 PWM B trigger routed to Front End Control 5 DPWM1_B_TRIG_ EN R W 0 Enables DPWM Trigger from DPWM 1 PWM B to Front End Control 0 DPWM 1 PWM B trigger not routed to Front End Control Default 1 DPWM 1 PWM B trigger routed to Front End Control 4 DPWM0_B_TRIG_ EN R W 0 Enables DPWM Trigger from DPWM 0 PWM B to Front End Control 0 DPWM 0 PWM B trigger not routed to Front End Control Default ...

Page 193: ...ol 9 DPWM1_FRAME_ SYNC_EN R W 0 Enables DPWM Trigger from DPWM 1 Frame Sync to Front End Control 0 DPWM 1 Frame Sync not routed to Front End Control Default 1 DPWM 1 Frame Sync routed to Front End Control 8 DPWM0_FRAME_ SYNC_EN R W 0 Enables DPWM Trigger from DPWM 0 Frame Sync to Front End Control 0 DPWM 0 Frame Sync not routed to Front End Control Default 1 DPWM 0 Frame Sync routed to Front End C...

Page 194: ...ptions continued Bit Field Type Reset Description 1 DPWM1_A_TRIG_ EN R W 0 Enables DPWM Trigger from DPWM 1 PWM B to Front End Control 0 DPWM 1 PWM A trigger not routed to Front End Control Default 1 DPWM 1 PWM A trigger routed to Front End Control 0 DPWM0_A_TRIG_ EN R W 0 Enables DPWM Trigger from DPWM 0 PWM B to Front End Control 0 DPWM 0 PWM A trigger not routed to Front End Control Default 1 D...

Page 195: ...ol 9 DPWM1_FRAME_ SYNC_EN R W 0 Enables DPWM Trigger from DPWM 1 Frame Sync to Front End Control 0 DPWM 1 Frame Sync not routed to Front End Control Default 1 DPWM 1 Frame Sync routed to Front End Control 8 DPWM0_FRAME_ SYNC_EN R W 0 Enables DPWM Trigger from DPWM 0 Frame Sync to Front End Control 0 DPWM 0 Frame Sync not routed to Front End Control Default 1 DPWM 0 Frame Sync routed to Front End C...

Page 196: ...ptions continued Bit Field Type Reset Description 1 DPWM1_A_TRIG_ EN R W 0 Enables DPWM Trigger from DPWM 1 PWM B to Front End Control 0 DPWM 1 PWM A trigger not routed to Front End Control Default 1 DPWM 1 PWM A trigger routed to Front End Control 0 DPWM0_A_TRIG_ EN R W 0 Enables DPWM Trigger from DPWM 0 PWM B to Front End Control 0 DPWM 0 PWM A trigger not routed to Front End Control Default 1 D...

Page 197: ... to Front End Control 2 Default 1 DPWM 0 Sample Trigger routed to Front End Control 2 7 FE1_TRIG_ DPWM3_EN R W 0 Enables Sample Trigger from DPWM 3 to Front End Control 1 0 DPWM 3 Sample Trigger not routed to Front End Control 1 Default 1 DPWM 3 Sample Trigger routed to Front End Control 1 6 FE1_TRIG_ DPWM2_EN R W 0 Enables Sample Trigger from DPWM 2 to Front End Control 1 0 DPWM 2 Sample Trigger ...

Page 198: ...00 Configures DAC 1 setpoint in External DAC Mode 0 DAC 0 Setpoint Selected Default 2 DAC 2 Setpoint Selected 3 Output of Constant Power Module Selected 4 Filter 0 Output Selected 5 Filter 1 Output Selected 6 Filter 2 Output Selected 15 11 Reserved R 0 0000 10 8 DAC0_SEL R W 000 Configures DAC 0 setpoint in External DAC Mode 1 DAC 1 Setpoint Selected 2 DAC 2 Setpoint Selected 3 Output of Constant ...

Page 199: ... Module 0 KComp 0 Value Selected Default 1 KComp 1 Value Selected 2 KComp 2 Value Selected 27 26 FILTER1_KCOMP _SEL R W 00 Selects KComp value routed to Filter 1 Module 0 KComp 0 Value Selected Default 1 KComp 1 Value Selected 2 KComp 2 Value Selected 25 24 FILTER0_KCOMP _SEL R W 00 Selects KComp value routed to Filter 0 Module 0 KComp 0 Value Selected Default 1 KComp 1 Value Selected 2 KComp 2 Va...

Page 200: ...Default 1 DPWM 1 Switching Period 2 DPWM 2 Switching Period 3 DPWM 3 Switching Period 7 6 Reserved R 5 4 FILTER2_FE_SEL R W 10 Selects which Front End Module provides data for Filter 2 Module 0 Front End Module 0 provides data to Filter 1 Front End Module 1 provides data to Filter 2 Front End Module 2 provides data to Filter Default 3 2 FILTER1_FE_SEL R W 01 Selects which Front End Module provides...

Page 201: ...OMP1 Reserved KCOMP0 R W 00 0000 0000 0000 R 00 R W 00 0000 0111 1101 LEGEND R W Read Write R Read only n value after reset Table 5 8 Filter KComp A Register FILTERKCOMPA Register Field Descriptions Bit Field Type Reset Description 29 16 KCOMP1 R W 00 0000 0000 0000 14 bit value used in filter output calculations replacing the DPWM switching period value 15 14 Reserved R 00 13 0 KCOMP0 R W 00 0000...

Page 202: ...er FILTERKCOMPB Address 0002001C Figure 5 9 Filter KComp B Register FILTERKCOMPB 13 0 KCOMP2 R W 00 0000 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 5 9 Filter KComp B Register FILTERKCOMPB Register Field Descriptions Bit Field Type Reset Description 13 0 KCOMP2 R W 00 0000 0000 0000 14 bit value used in filter output calculations replacing the DPWM switching period value...

Page 203: ...End 1 Ramp output selected 2 Front End 2 Ramp output selected 29 28 DPWM2_SYNC _FET_SEL R W 00 Selects Ramp source for DPWM2 PWM B SyncFET soft on off 0 Front End 0 Ramp output selected Default 1 Front End 1 Ramp output selected 2 Front End 2 Ramp output selected 27 26 DPWM1_SYNC _FET_SEL R W 00 Selects Ramp source for DPWM1 PWM B SyncFET soft on off 0 Front End 0 Ramp output selected Default 1 Fr...

Page 204: ... DPWM_ON_TIME value from Light Load Control Register 8 6 DPWM2_FILTER _SEL R W 010 Selects source of duty cycle resonant period for DPWM Module 2 0 Filter 0 Output Selected Default 1 Filter 1 Output Selected 2 Filter 2 Output Selected 3 Constant Power Module Selected 4 DPWM_ON_TIME value from Light Load Control Register 5 3 DPWM1_FILTER _SEL R W 001 Selects source of duty cycle resonant period for...

Page 205: ...3 LOWER_COMP _EN R W 0 Enables output of lowest duty from current or voltage loop when Constant Power Constant Current module controls loop output 0 Loop output controlled by mode selection voltage loop selected in constant voltage and constant power mode current loop selected in constant current mode Default 1 Loop output controlled by lowest duty from voltage or current loops 12 VLOOP_FREEZE _EN...

Page 206: ...CPC_INT_EN R W 0 Constant Power Constant Current Interrupt Enable 0 Interrupt disabled on mode switches Default 1 Interrupt enabled on mode switches 1 CPCC_CONFIG R W 0 Controls Constant Power Constant Current module configuration 0 Average Current Mode Default 1 Constant Power Module controls selection of voltage current loop 0 CPCC_EN R W 0 Constant Power Constant Current Module Enable 0 Constan...

Page 207: ...ead only n value after reset Table 5 12 Constant Power Nominal Threshold Register CPNOM Register Field Descriptions Bit Field Type Reset Description 25 16 NOM_CURRENT_ UPPER R W 00 0000 0000 Configures INOM value used in Constant Power Constant Current Calculations when sensed value exceeds NOM_CURRENT_UPPER in Constant Voltage mode setpoint will switch to Constant Power mode 15 10 Reserved R 00 0...

Page 208: ...R Read only n value after reset Table 5 13 Constant Power Max Threshold Register CPMAX Register Field Descriptions Bit Field Type Reset Description 25 16 MAX_CURRENT_ UPPER R W 00 0000 0000 Configures IMAX value used in Constant Power Constant Current Calculations when sensed value exceeds MAX_CURRENT_UPPER in Constant Power mode setpoint will switch to Max Current mode 15 10 Reserved R 00 0000 9 ...

Page 209: ...AGE R W 00 0000 0000 R 00 0000 R W 00 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 5 14 Constant Power Configuration Register CPCONFIG Register Field Descriptions Bit Field Type Reset Description 25 16 MAX_CURRENT R W 00 0000 0000 Configures IMAX setpoint used in Constant Power Constant Current Calculations in Max Current mode 15 10 Reserved R 00 0000 9 0 NOM_VOLTAGE R W 0...

Page 210: ...ddress 00020034 Figure 5 15 Constant Power Max Power Register CPMAXPWR 19 0 MAX_POWER R W 0000 0000 0000 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 5 15 Constant Power Max Power Register CPMAXPWR Register Field Descriptions Bit Field Type Reset Description 19 0 MAX_POWER R W 0000 0000 0000 0000 0000 Configures PMAX value used in Constant Power Constant Current calculatio...

Page 211: ...038 Figure 5 16 Constant Power Integrator Threshold Register CPINTTHRESH 23 0 INT_THRESH R W 0000 0000 0000 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 5 16 Constant Power Integrator Threshold Register CPINTTHRESH Register Field Descriptions Bit Field Type Reset Description 23 0 INT_THRESH R W 0000 0000 0000 0000 0000 24 bit signed value added to Current Loop Duty value t...

Page 212: ...0002003C Figure 5 17 Constant Power Firmware Divisor Register CPFWDIVISOR 9 0 FW_DIVISOR R W 00 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 5 17 Constant Power Firmware Divisor Register CPFWDIVISOR Register Field Descriptions Bit Field Type Reset Description 9 0 FW_DIVISOR R W 00 0000 0000 10 bit value used in Constant Power calculation when firmware value is selected in ...

Page 213: ...s cleared on read 0 No transition from Constant Current to Constant Voltage detected 1 Transition from Constant Current to Constant Voltage detected 4 CC_TO_CC_INT R 0 Constant Voltage Mode to Constant Current Mode latched status cleared on read 0 No transition from Constant Voltage to Constant Current detected 1 Transition from Constant Voltage to Constant Current detected 3 CV_TO_CC_INT R 0 Cons...

Page 214: ...128x gain 6 5 CYC_ADJ_SYNC R W 00 Selects which DPWM A trigger synchronizes cycle adjustment calculation first 2 samples after receipt of DPWM A trigger will be used for Cycle Adjustment Calculation 0 DPWM 1A trigger selected Default 1 DPWM 2A trigger selected 2 DPWM 3A trigger selected 3 DPWM 4A trigger selected 4 3 SECOND _SAMPLE_SEL R W 00 Configures Front End Module Data used for Second Sample...

Page 215: ...ycle Adjustment Limit Register CYCADJLIM Register Field Descriptions Bit Field Type Reset Description 28 16 CYC_ADJ _UPPER_LIMIT R W 0 0000 0000 0000 Cycle Adjustment Calculation signed upper limit value output of Cycle Adjustment Calculation is clamped at the upper limit if calculated result exceeds the upper limit LSB resolution equals High Frequency Oscillator period 16 15 13 Reserved R 000 12 ...

Page 216: ... 10 9 0 CYC_ADJ_CALC Reserved CYC_ADJ_ERROR R 0 R 00 0000 R 0 LEGEND R W Read Write R Read only n value after reset Table 5 21 Cycle Adjustment Status Register CYCADJSTAT Register Field Descriptions Bit Field Type Reset Description 28 16 CYC_ADJ_CALC R 0 13 bit signed value representing calculated Cycle Adjustment provided to DPWM module based on first 2 error samples 15 10 Reserved R 00 0000 9 0 ...

Page 217: ...d Control 2 Module Disabled Default 1 Front End Control 2 Module Enabled 9 FE_CTRL1_EN R W 0 Global Firmware Enable for Front End Control 1 Module 0 Front End Control 1 Module Disabled Default 1 Front End Control 1 Module Enabled 8 FE_CTRL0_EN R W 0 Global Firmware Enable for Front End Control 0 Module 0 Front End Control 0 Module Disabled Default 1 Front End Control 0 Module Enabled 7 4 Reserved ...

Page 218: ...54 Figure 5 23 PWM Global Period Register PWMGLBPRD 17 4 3 0 PRD Reserved R W 00 0000 0000 0000 R 0000 LEGEND R W Read Write R Read only n value after reset Table 5 23 PWM Global Period Register PWMGLBPRD Register Field Descriptions Bit Field Type Reset Description 17 4 PRD R W 00 0000 0000 0000 Global PWM Period value overriding DPWM Period settings when global PWM period is selected within each ...

Page 219: ...N R 0 Value of Sync pin 0 Logic level low present on Sync pin 1 Logic level high present on Sync pin 4 2 SYNC_MUX_SEL R W 000 Selects which module controls Sync pin output 000 DPWM 0 Sync Output Default 001 DPWM 1 Sync Output 010 DPWM 2 Sync Output 011 DPWM 3 Sync Output 100 Value from SYNC_OUT Bit 1 101 Value from CLKOUT signal in TSAR Module See Section 15 1 110 Low Frequency Oscillator Clock Ou...

Page 220: ... Field Descriptions Bit Field Type Reset Description 25 8 DPWM_ON_TIME R W 00 0000 0000 0000 0000 DPWM pulse width used for EADC based light load mode operation when selected Filter data exceeds TURN_ON_THRESH value 7 4 Reserved R 0000 3 CYCLE_CNT_EN R W 0 Enables Switching Cycle Counter for enabling constant pulse widths when configured in Light Load operation 0 Switching Cycle Counter disabled D...

Page 221: ...0000 0000 R 0000 00 R W 00 0000 0000 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 5 26 Light Load Enable Threshold Register LLENTHRESH Register Field Descriptions Bit Field Type Reset Description 31 24 CYCLE_CNT _THRESH R W 0000 0000 Switching Cycle threshold where constant width DPWM pulses are enabled when number of switching cycles without pulses exceeds threshold 23 18...

Page 222: ...64 Figure 5 27 Light Load Disable Threshold Register LLDISTHRESH 17 0 TURN_OFF_THRESH R W 00 0000 0000 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 5 27 Light Load Disable Threshold Register LLDISTHRESH Register Field Descriptions Bit Field Type Reset Description 17 0 TURN_OFF _THRESH R W 00 0000 0000 0000 0000 Filter data threshold where constant width DPWM pulses are dis...

Page 223: ...rol Register PCMCTRL 5 4 3 0 PCM_FILTER_SEL Reserved R W 00 R 0000 LEGEND R W Read Write R Read only n value after reset Table 5 28 Peak Current Mode Control Register PCMCTRL Register Field Descriptions Bit Field Type Reset Description 5 4 PCM_FILTER _SEL R W 00 Selects source of Peak Current Slope Compensation Ramp Start 0 Filter 0 data selected Default 1 Filter 1 data selected 2 Filter 2 data se...

Page 224: ...er APCMCTRL Register Field Descriptions Bit Field Type Reset Description 3 PCM_LATCH_EN R W 0 Enables latching of Peak Current Flag to end of frame 0 PCM Flag is not latched to end of PCM Frame Default 1 PCM Flag is latched to end of PCM Frame 2 1 PCM_FE_SEL R W 00 Selects source of Front End Comparator output for Analog Peak Current Mode Control 0 Front End Control 0 Comparator output selected De...

Page 225: ...oop BIST Complete Status 0 High Speed Loop BIST not complete 1 High Speed Loop BIST completed 17 BIST_EN R W 0 High Speed Loop BIST Enable 0 High Speed Loop BIST disabled Default 1 High Speed Loop BIST enabled 16 EADC_TRIM _TEST_EN R W 0 EADC Trim Test Mode Enable 0 EADC Trim Test Mode disabled Default 1 EADC Trim Test Mode enabled bits 15 0 provided to all 3 Analog Front End modules 15 10 EADC_RE...

Page 226: ... The Fault Mux registers control a multiplexer which connects power supply fault signals to DPWMs They also perform several other functions Configuration of analog and digital comparators and fault pins for fault detection Monitoring of fault status Digital Ideal Diode Emulation circuit for synchronous rectification FETs Processor clock failure detection Support for analog peak current mode contro...

Page 227: ...gital fault pin can be all mapped to a fault A signal connected to a single DPWM fault input and shut down DPWM1 A 2 Single fault output mapped to many fault inputs inside many DPWM modules An analog comparator in charge of over current protection can be mapped to all DPWM 0 through DPWM 3 through several fault modules 3 Many fault sources mapped to a many fault modules inside many DPWM modules A ...

Page 228: ... ACOMPCTRL0 bit ACOMP_EN 1 This bit enables all the analog comparators 6 1 2 ACOMP_x_THRESH For typical operation detecting an overcurrent or over voltage fault only the ACOMP_x_THRESH register needs to be written It is written with a value that corresponds to the fault level on the input pin FaultMuxRegs ACOMPCTRL1 bit ACOMP_C_THRESH OVER_VOLTAGE_THRESH All the other registers are set to defaults...

Page 229: ... End is used as a source and whether the absolute or error data from that Front End is used Like the Analog Comparators they can be programmed to detect a fault either above or below the threshold The COMP_POL bit is used to select this There is also an INT_EN bit to enable the interrupt Each Digital Comparator has its own COMP_EN bit to enable it The reference threshold for the comparator is much...

Page 230: ...ured since the last read of FAULTMUXINTSTAT Have interrupts enabled This is especially useful for detecting faults which may occur only for short times during a period Reading from this register clears the fault from the fault detection interrupt logic This interrupt logic is independent of the signals routed to the Fault Mux and to the DPWM These signals are latched only in the DPWM logic not any...

Page 231: ...tion Figure 6 3 UCD3138 DPWM Fault Action This drawing fits in with the overview of the DPWM in Figure 2 1 The portion expanded here is the fault handler portion The connection of the CLIM CBC signal to the Timing Generation Module is also shown For information on the effect of CLIM CBC in the timing module see Section 2 15 3 The bits described in that section affect the CLIM CBC signal which is s...

Page 232: ...M_EN 1 The DPWMINT register can be used to configure Fault interrupts as well as other interrupts It can also be used to read the status of those interrupts The interrupt bits are cleared by a read The DPWMFLTSTAT register shows the status of the faults These bits are also clear on read bits See the reference section for bit mapping of these registers If the fault is enabled by the ALL_FAULT_EN bi...

Page 233: ...dule The DPWM module is selected by the LoopMux FILTERMUX bit FILTERx_PER_SEL bitfield as shown below Figure 6 4 Normally FILTERx_PER_SEL will already be pointing at the right Filter because it is also used to provide the period for the Filter to use in calculating the duty value In some cases however for example where KCOMP is used instead of period it is still necessary to set FILTERx_PER_SEL so...

Page 234: ... 0 HFO_DETECT_EN a 1 enables High Frequency Oscillator Failure Detection logic device will be reset upon detection of an oscillator failure here is no interrupt or status bit for HFO failure This is because if the HFO fails the processor will not be working 6 10 2 Low Frequency Oscillator Failure Detection The Low Frequency Oscillator is used for the watchdog timer and to test the functionality of...

Page 235: ...by Comparator Ramp 0 2 Analog Comparator B Threshold set by Filter 0 Output 3 Analog Comparator B Threshold set by Filter 1 Output 4 Analog Comparator B Threshold set by Filter 2 Output 18 ACOMP_B_POL R W 1 Analog Comparator B Polarity 0 Comparator result enabled when input falls below threshold 1 Comparator result enabled when input exceeds threshold Default 17 ACOMP_B_INT_ EN R W 0 Analog Compar...

Page 236: ...omparator Control 0 Register ACOMPCTRL0 Register Field Descriptions continued Bit Field Type Reset Description 1 ACOMP_A_INT_ EN R W 0 Analog Comparator A Interrupt Enable 0 Disables Analog Comparator A Interrupt generation Default 1 Enables Analog Comparator A Interrupt generation 0 ACOMP_EN R W 0 Analog Comparators Enable 0 Analog Comparators Disabled Default 1 Analog Comparators Enabled ...

Page 237: ...Comparator Reference of 2 5 V 23 22 Reserved R 00 21 19 ACOMP_D_SEL R W 000 Configures Analog Comparator D Threshold 0 Analog Comparator D Threshold set by ACOMP_D_THRESH Default 1 Analog Comparator D Threshold set by Comparator Ramp 0 2 Analog Comparator D Threshold set by Filter 0 Output 3 Analog Comparator D Threshold set by Filter 1 Output 4 Analog Comparator D Threshold set by Filter 2 Output...

Page 238: ... ACOMP_C_THRESH Default 1 Analog Comparator C Threshold set by Comparator Ramp 0 2 Analog Comparator C Threshold set by Filter 0 Output 3 Analog Comparator C Threshold set by Filter 1 Output 4 Analog Comparator C Threshold set by Filter 2 Output 2 ACOMP_C_POL R W 1 Analog Comparator C Polarity 0 Comparator result enabled when input falls below threshold 1 Comparator result enabled when input excee...

Page 239: ..._REF_ SEL R W 0 Analog Comparator F Reference Select 0 Selects internal DAC reference Default 1 Selects reference driven from AD 07 pin 21 19 ACOMP_F_SEL R W 000 Configures Analog Comparator F Threshold 0 Analog Comparator F Threshold set by ACOMP_F_THRESH Default 1 Analog Comparator F Threshold set by Comparator Ramp 0 2 Analog Comparator F Threshold set by Filter 0 Output 3 Analog Comparator F T...

Page 240: ...p 0 2 Analog Comparator E Threshold set by Filter 0 Output 3 Analog Comparator E Threshold set by Filter 1 Output 4 Analog Comparator E Threshold set by Filter 2 Output 2 ACOMP_E_POL R W 1 Analog Comparator E Polarity 0 Comparator result enabled when input falls below threshold 1 Comparator result enabled when input exceeds threshold Default 1 ACOMP_E_INT _EN R W 0 Analog Comparator E Interrupt En...

Page 241: ...parator Reference of 39 0625 mV 127 Comparator Reference of 2 5 V 7 6 Reserved R 00 5 3 ACOMP_G_SEL R W 000 Configures Analog Comparator G Threshold 0 Analog Comparator G Threshold set by ACOMP_G_THRESH Default 1 Analog Comparator G Threshold set by Comparator Ramp 0 2 Analog Comparator G Threshold set by Filter 0 Output 3 Analog Comparator G Threshold set by Filter 1 Output 4 Analog Comparator G ...

Page 242: ... detection enabled on falling edge 1 Fault detection enabled on rising edge Default 8 FAULT0_POL R W 1 Polarity configuration for FAULT 0 pin 0 Fault detection enabled on falling edge 1 Fault detection enabled on rising edge Default 7 FAULT3_INT_EN R W 0 FAULT 3 Pin Interrupt Enable 0 Disables Fault Detection Interrupt generation Default 1 Enables Fault Detection Interrupt generation 6 FAULT2_INT_...

Page 243: ...nactive 1 Comparator threshold interrupt active 13 DCOMP0 R 0 Digital Comparator 0 Interrupt Status cleared by read of status register 0 Comparator threshold interrupt inactive 1 Comparator threshold interrupt active 12 LFO_FAIL R 0 Low Frequency Oscillator Failure Interrupt Status cleared by read of status register 0 Low Frequency Oscillator operational 1 Low Frequency Oscillator failure detected...

Page 244: ...e 3 ACOMP_D R 0 Analog Comparator D Interrupt Status cleared by read of status register 0 Comparator threshold interrupt inactive 1 Comparator threshold interrupt active 2 ACOMP_C R 0 Analog Comparator C Interrupt Status cleared by read of status register 0 Comparator threshold interrupt inactive 1 Comparator threshold interrupt active 1 ACOMP_B R 0 Analog Comparator B Interrupt Status cleared by ...

Page 245: ...0 Comparator threshold not exceeded 1 Comparator threshold exceeded 13 DCOMP0 R 0 Digital Comparator 0 Raw Status 0 Comparator threshold not exceeded 1 Comparator threshold exceeded 12 LFO_FAIL R 0 Low Frequency Oscillator Failure Raw Status 0 Low Frequency Oscillator operationaL 1 Low Frequency Oscillator failure detected 11 FAULT3 R 0 External Fault Detection on FAULT 3 pin 0 No External FAULT 3...

Page 246: ... E Raw Result 0 Comparator threshold not exceeded 1 Comparator threshold exceeded 3 ACOMP_D R 0 Analog Comparator D Raw Result 0 Comparator threshold not exceeded 1 Comparator threshold exceeded 2 ACOMP_C R 0 Analog Comparator C Raw Result 0 Comparator threshold not exceeded 1 Comparator threshold exceeded 1 ACOMP_B R 0 Analog Comparator B Raw Result 0 Comparator threshold not exceeded 1 Comparato...

Page 247: ...lue 6 Analog Comparator Threshold D Value 7 Analog Comparator Threshold E Value 8 Analog Comparator Threshold F Value 9 Analog Comparator Threshold G Value 27 10 STEP_SIZE R W 00 0000 0000 0000 0000 Programmable 18 bit unsigned comparator step with Bits 27 24 representing the integer portion of the comparator step 0 15 Comparator steps of 19 5mV each and Bits 23 10 representing the fractional port...

Page 248: ...ister COMPRAMP0 Register Field Descriptions continued Bit Field Type Reset Description 1 DPWM0_TRIG _EN R W 0 Enables DPWM Trigger from DPWM 0 to Analog Comparator Ramp 0 0 DPWM 0 trigger not routed to Analog Comparator Ramp 0 Default 1 DPWM 0 trigger routed to Analog Comparator Ramp 0 0 RAMP_EN R W 0 Enable for Analog Comparator Ramp 0 0 Analog Comparator Ramp disabled Default 1 Analog Comparator...

Page 249: ...Comparator result asserted if value above threshold 17 15 FE_SEL R W 000 Selects which Front End absolute data is used for Digital Comparison with threshold 0 Front End 0 absolute data selected Default 1 Front End 1 absolute data selected 2 Front End 2 absolute data selected 3 Front End 0 error data selected 4 Front End 1 error data selected 5 Front End 2 error data selected 14 CNT_CLR R W 0 Compa...

Page 250: ... Comparator result asserted if value above threshold 17 15 FE_SEL R W 000 Selects which Front End absolute data is used for Digital Comparison with threshold 0 Front End 0 absolute data selected Default 1 Front End 1 absolute data selected 2 Front End 2 absolute data selected 3 Front End 0 error data selected 4 Front End 1 error data selected 5 Front End 2 error data selected 14 CNT_CLR R W 0 Comp...

Page 251: ... Comparator result asserted if value above threshold 17 15 FE_SEL R W 000 Selects which Front End absolute data is used for Digital Comparison with threshold 0 Front End 0 absolute data selected Default 1 Front End 1 absolute data selected 2 Front End 2 absolute data selected 3 Front End 0 error data selected 4 Front End 1 error data selected 5 Front End 2 error data selected 14 CNT_CLR R W 0 Comp...

Page 252: ... Comparator result asserted if value above threshold 17 15 FE_SEL R W 000 Selects which Front End absolute data is used for Digital Comparison with threshold 0 Front End 0 absolute data selected Default 1 Front End 1 absolute data selected 2 Front End 2 absolute data selected 3 Front End 0 error data selected 4 Front End 1 error data selected 5 Front End 2 error data selected 14 CNT_CLR R W 0 Comp...

Page 253: ...DCOMP3_CNT DCOMP2_CNT DCOMP1_CNT DCOMP0_CNT R 0 R 0 R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 6 13 Digital Comparator Counter Status Register DCOMPCNTSTAT Register Field Descriptions Bit Field Type Reset Description 31 24 DCOMP3_CNT R 0 Current value of Digital Comparator 3 detection counter 23 16 DCOMP2_CNT R 0 Current value of Digital Comparator 2 detection counter 15 8...

Page 254: ...Enables Digital Comparator 1 result for DPWM 0 Current Limit 0 Digital Comparator 1 result disabled for current limit Default 1 Digital Comparator 1 result enabled for current limit 12 DCOMP0_EN R W 0 Enables Digital Comparator 0 result for DPWM 0 Current Limit 0 Digital Comparator 0 result disabled for current limit Default 1 Digital Comparator 0 result enabled for current limit 11 Reserved R 0 1...

Page 255: ...fault 1 Analog Comparator result enabled for current limit 2 ACOMP_C_EN R W 0 Enables Analog Comparator C result for DPWM 0 Current Limit 0 Analog Comparator result disabled for current limit Default 1 Analog Comparator result enabled for current limit 1 ACOMP_B_EN R W 0 Enables Analog Comparator B result for DPWM 0 Current Limit 0 Analog Comparator result disabled for current limit Default 1 Anal...

Page 256: ...R W 0 R W 0 R W 0 7 6 5 4 3 2 1 0 FAULT0_EN ACOMP_G_EN ACOMP_F_EN ACOMP_E_EN ACOMP_D_EN ACOMP_C_EN ACOMP_B_EN ACOMP_A_EN R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 6 15 DPWM 0 Fault AB Detection Register DPWM0FLTABDET Register Field Descriptions Bit Field Type Reset Description 14 DCOMP3_EN R W 0 13 DCOMP2_EN R W 0 12 DCOMP1_EN R W 0...

Page 257: ...al Comparator 3 enabled for fault detection 29 PWMB_DCOMP 2_EN R W 0 Enables Digital Comparator 2 result for DPWM 0 PWM B Fault Detection 0 Digital Comparator 2 disabled for fault detection Default 1 Digital Comparator 2 enabled for fault detection 28 PWMB_DCOMP1 _EN R W 0 Enables Digital Comparator 1 result for DPWM 0 PWM B Fault Detection 0 Digital Comparator 1 disabled for fault detection Defau...

Page 258: ...mparator result disabled for fault detection Default 1 Analog Comparator result enabled for fault detection 14 PWMA_DCOMP3 _EN R W 0 Enables Digital Comparator 3 result for DPWM 0 PWM A Fault Detection 0 Digital Comparator 3 disabled for fault detection Default 1 Digital Comparator 3 enabled for fault detection 13 PWMA_DCOMP 2_EN R W 0 Enables Digital Comparator 2 result for DPWM 0 PWM A Fault Det...

Page 259: ...ator result enabled for fault detection 3 PWMA_ACOMP _D_EN R W 0 Enables Analog Comparator D result for DPWM 0 PWM A Fault detection 0 Analog Comparator result disabled for fault detection Default 1 Analog Comparator result enabled for fault detection 2 PWMA_ACOMP _C_EN R W 0 Enables Analog Comparator C result for DPWM 0 PWM A Fault detection 0 Analog Comparator result disabled for fault detection...

Page 260: ... Enables Digital Comparator 1 result for DPWM 2 Current Limit 0 Digital Comparator 1 result disabled for current limit Default 1 Digital Comparator 1 result enabled for current limit 12 DCOMP0_EN R W 0 Enables Digital Comparator 0 result for DPWM 2 Current Limit 0 Digital Comparator 0 result disabled for current limit Default 1 Digital Comparator 0 result enabled for current limit 11 Reserved R 0 ...

Page 261: ...fault 1 Analog Comparator result enabled for current limit 2 ACOMP_C_EN R W 0 Enables Analog Comparator C result for DPWM 2 Current Limit 0 Analog Comparator result disabled for current limit Default 1 Analog Comparator result enabled for current limit 1 ACOMP_B_EN R W 0 Enables Analog Comparator B result for DPWM 2 Current Limit 0 Analog Comparator result disabled for current limit Default 1 Anal...

Page 262: ... Comparator 0 result for DPWM 2 Current Limit 0 Digital Comparator 0 result disabled for current limit Default 1 Digital Comparator 0 result enabled for current limit 10 FAULT3_EN R W 0 Enables FAULT 3 pin for DPWM 2 Current Limit 0 External Fault pin disabled for current limit Default 1 External Fault pin enabled for current limit 9 FAULT2_EN R W 0 Enables FAULT 2 pin for DPWM 2 Current Limit 0 E...

Page 263: ...arator C result for DPWM 2 Current Limit 0 Analog Comparator result disabled for current limit Default 1 Analog Comparator result enabled for current limit 1 ACOMP_B_EN R W 0 Enables Analog Comparator B result for DPWM 2 Current Limit 0 Analog Comparator result disabled for current limit Default 1 Analog Comparator result enabled for current limit 0 ACOMP_A_EN R W 0 Enables Analog Comparator A res...

Page 264: ...al Comparator 3 enabled for fault detection 29 PWMB_DCOMP2 _EN R W 0 Enables Digital Comparator 2 result for DPWM 0 PWM B Fault Detection 0 Digital Comparator 2 disabled for fault detection Default 1 Digital Comparator 2 enabled for fault detection 28 PWMB_DCOMP1 _EN R W 0 Enables Digital Comparator 1 result for DPWM 0 PWM B Fault Detection 0 Digital Comparator 1 disabled for fault detection Defau...

Page 265: ...mparator result disabled for fault detection Default 1 Analog Comparator result enabled for fault detection 14 PWMA_DCOMP3 _EN R W 0 Enables Digital Comparator 3 result for DPWM 0 PWM A Fault Detection 0 Digital Comparator 3 disabled for fault detection Default 1 Digital Comparator 3 enabled for fault detection 13 PWMA_DCOMP2 _EN R W 0 Enables Digital Comparator 2 result for DPWM 0 PWM A Fault Det...

Page 266: ...ator result enabled for fault detection 3 PWMA_ACOMP _D_EN R W 0 Enables Analog Comparator D result for DPWM 0 PWM A Fault detection 0 Analog Comparator result disabled for fault detection Default 1 Analog Comparator result enabled for fault detection 2 PWMA_ACOMP _C_EN R W 0 Enables Analog Comparator C result for DPWM 0 PWM A Fault detection 0 Analog Comparator result disabled for fault detection...

Page 267: ... Enables Digital Comparator 1 result for DPWM 2 Current Limit 0 Digital Comparator 1 result disabled for current limit Default 1 Digital Comparator 1 result enabled for current limit 12 DCOMP0_EN R W 0 Enables Digital Comparator 0 result for DPWM 2 Current Limit 0 Digital Comparator 0 result disabled for current limit Default 1 Digital Comparator 0 result enabled for current limit 11 Reserved R 0 ...

Page 268: ...fault 1 Analog Comparator result enabled for current limit 2 ACOMP_C_EN R W 0 Enables Analog Comparator C result for DPWM 2 Current Limit 0 Analog Comparator result disabled for current limit Default 1 Analog Comparator result enabled for current limit 1 ACOMP_B_EN R W 0 Enables Analog Comparator B result for DPWM 2 Current Limit 0 Analog Comparator result disabled for current limit Default 1 Anal...

Page 269: ... Comparator 0 disabled for Fault AB detection Default 1 Digital Comparator 0 enabled for Fault AB detection 10 FAULT3_EN R W 0 Enables FAULT 3 pin for DPWM 2 Fault AB detection 0 External Fault pin disabled for Fault AB detection Default 1 External Fault pin enabled for Fault AB detection 9 FAULT2_EN R W 0 Enables FAULT 2 pin for DPWM 2 Fault AB detection 0 External Fault pin disabled for Fault AB...

Page 270: ...WM 2 Fault AB detection 0 Analog Comparator result disabled for Fault AB detection Default 1 Analog Comparator result enabled for Fault AB detection 1 ACOMP_B_EN R W 0 Enables Analog Comparator B result for DPWM 2 Fault AB detection 0 Analog Comparator result disabled for Fault AB detection Default 1 Analog Comparator result enabled for Fault AB detection 0 ACOMP_A_EN R W 0 Enables Analog Comparat...

Page 271: ...ault 1 Digital Comparator 3 enabled for fault detection 29 PWMB_DCOMP2 _EN R W 0 Enables Digital Comparator 2 result for DPWM 2 PWM B Fault Detection 0 Digital Comparator 2 disabled for fault detection Default 1 Digital Comparator 2 enabled for fault detection 28 PWMB_DCOMP1 _EN R W 0 Enables Digital Comparator 1 result for DPWM 2 PWM B Fault Detection 0 Digital Comparator 1 disabled for fault det...

Page 272: ...n 0 Digital Comparator 3 disabled for fault detection Default 1 Digital Comparator 3 enabled for fault detection 13 PWMA_DCOMP2 _EN R W 0 Enables Digital Comparator 2 result for DPWM 2 PWM A Fault Detection 0 Digital Comparator 2 disabled for fault detection Default 1 Digital Comparator 2 enabled for fault detection 12 PWMA_DCOMP1 _EN R W 0 Enables Digital Comparator 1 result for DPWM 2 PWM A Faul...

Page 273: ...WM 2 PWM A Fault detection 0 Analog Comparator result disabled for fault detection Default 1 Analog Comparator result enabled for fault detection 2 PWMA_ACOMP _C_EN R W 0 Enables Analog Comparator C result for DPWM 2 PWM A Fault detection 0 Analog Comparator result disabled for fault detection Default 1 Analog Comparator result enabled for fault detection 1 PWMA_ACOMP _B_EN R W 0 Enables Analog Co...

Page 274: ...Enables Digital Comparator 1 result for DPWM 3 Current Limit 0 Digital Comparator 1 result disabled for current limit Default 1 Digital Comparator 1 result enabled for current limit 12 DCOMP0_EN R W 0 Enables Digital Comparator 0 result for DPWM 3 Current Limit 0 Digital Comparator 0 result disabled for current limit Default 1 Digital Comparator 0 result enabled for current limit 11 Reserved R 0 1...

Page 275: ...fault 1 Analog Comparator result enabled for current limit 2 ACOMP_C_EN R W 0 Enables Analog Comparator C result for DPWM 3 Current Limit 0 Analog Comparator result disabled for current limit Default 1 Analog Comparator result enabled for current limit 1 ACOMP_B_EN R W 0 Enables Analog Comparator B result for DPWM 3 Current Limit 0 Analog Comparator result disabled for current limit Default 1 Anal...

Page 276: ... Comparator 0 disabled for Fault AB detection Default 1 Digital Comparator 0 enabled for Fault AB detection 10 FAULT3_EN R W 0 Enables FAULT 3 pin for DPWM 3 Fault AB detection 0 External Fault pin disabled for Fault AB detection Default 1 External Fault pin enabled for Fault AB detection 9 FAULT2_EN R W 0 Enables FAULT 2 pin for DPWM 3 Fault AB detection 0 External Fault pin disabled for Fault AB...

Page 277: ...WM 3 Fault AB detection 0 Analog Comparator result disabled for Fault AB detection Default 1 Analog Comparator result enabled for Fault AB detection 1 ACOMP_B_EN R W 0 Enables Analog Comparator B result for DPWM 3 Fault AB detection 0 Analog Comparator result disabled for Fault AB detection Default 1 Analog Comparator result enabled for Fault AB detection 0 ACOMP_A_EN R W 0 Enables Analog Comparat...

Page 278: ...l Comparator 3 enabled for fault detection 29 PWMB_DCOMP2 _EN R W 0 Enables Digital Comparator 2 result for DPWM 3 PWM B Fault Detection 0 Digital Comparator 2 disabled for fault detection Default 1 Digital Comparator 2 enabled for fault detection 28 PWMB_DCOMP1 _EN R W 0 Enables Digital Comparator 1 result for DPWM 3 PWM B Fault Detection 0 Digital Comparator 1 disabled for fault detection Defaul...

Page 279: ...n 0 Digital Comparator 3 disabled for fault detection Default 1 Digital Comparator 3 enabled for fault detection 13 PWMA_DCOMP2 _EN R W 0 Enables Digital Comparator 2 result for DPWM 3 PWM A Fault Detection 0 Digital Comparator 2 disabled for fault detection Default 1 Digital Comparator 2 enabled for fault detection 12 PWMA_DCOMP1 _EN R W 0 Enables Digital Comparator 1 result for DPWM 3 PWM A Faul...

Page 280: ...WM 3 PWM A Fault detection 0 Analog Comparator result disabled for fault detection Default 1 Analog Comparator result enabled for fault detection 2 PWMA_ACOMP _C_EN R W 0 Enables Analog Comparator C result for DPWM 3 PWM A Fault detection 0 Analog Comparator result disabled for fault detection Default 1 Analog Comparator result enabled for fault detection 1 PWMA_ACOMP _B_EN R W 0 Enables Analog Co...

Page 281: ...O Fail Detect Register HFOFAILDET Register Field Descriptions Bit Field Type Reset Description 17 1 HFO_FAIL _THRESH R W 0 0000 0000 1111 1111 Configures threshold where a clear flag is used to clear a counter in the Low Frequency Oscillator domain if LFO counter overflows a reset will be generated resolution of threshold equals High Frequency Oscillator period 0 HFO_DETECT _EN R W 0 Enables High ...

Page 282: ...ription 6 2 LFO_FAIL _THRESH R W 0 0011 Configures threshold where a clear flag is used to clear a counter in the High Frequency Oscillator domain if HFO counter overflows a reset will be generated resolution of threshold equals Low Frequency Oscillator period 1 LFO_FAIL_INT _EN R W 0 Low Frequency Oscillator Fail Interrupt Enable 0 Disables Interrupt Generation upon LFO Failure Detection Default ...

Page 283: ...ister Field Descriptions Bit Field Type Reset Description 31 24 DCM_LIMIT_H R W 0000 0000 Value added to 1 Da value to provide hysteresis for exiting DCM mode 23 16 DCM_LIMIT_L R W 0000 0000 Value subtracted from 1 Da value to provide hysteresis for entering DCM mode 15 14 Reserved R 00 13 DCM_INT_EN R W 0 Enables Discontinuous Conduction Mode DCM interrupt generation based on selected Filter outp...

Page 284: ...d boundaries Byte Half word and Word Writes are permitted All Registers can be read in any mode All Registers are writeable Topic Page 7 1 Fault IO Direction Register FAULTDIR 285 7 2 Fault Input Register FAULTIN 286 7 3 Fault Output Register FAULTOUT 287 7 4 Fault Interrupt Enable Register FAULTINTENA 288 7 5 Fault Interrupt Polarity Register FAULTINTPOL 289 7 6 Fault Interrupt Pending Register F...

Page 285: ... configured as an output pin in GPIO mode 5 TDI_DIR R W 0 TDI Pin Configuration 0 TDI pin configured as an input pin in GPIO mode Default 1 TDI pin configured as an output pin in GPIO mode 4 TDO_DIR R W 0 TDO Pin Configuration 0 TDO pin configured as an input pin in GPIO mode Default 1 TDO pin configured as an output pin in GPIO mode 3 FLT3_DIR R W 0 FAULT 3 Pin Configuration 0 FAULT 3 pin configu...

Page 286: ...set Description 6 TMS_IN R 0 Input Value of TMS Pin 0 TMS pin driven low in GPIO mode 1 TMS pin driven high in GPIO mode 5 TDI_IN R 0 Input Value of TDI Pin 0 TDI pin driven low in GPIO mode 1 TDI pin driven high in GPIO mode 4 TDO_IN R 0 Input Value of TDO Pin 0 TDO pin driven low in GPIO mode 1 TDO pin driven high in GPIO mode 3 FLT3_IN R 0 Input Value of FAULT 3 Pin 0 FAULT 3 pin driven low 1 F...

Page 287: ...MS pin driven high when configured as output in GPIO mode 5 TDI_OUT R W 0 TDI Pin Output Value 0 TDI pin driven low when configured as output in GPIO mode Default 1 TDI pin driven high when configured as output in GPIO mode 4 Reserved R 0 3 FLT3_OUT R W 0 FAULT 3 Pin Output Value 0 FAULT 3 pin driven low when configured as output Default 1 FAULT 3 pin driven high when configured as output 2 FLT2_O...

Page 288: ...Enable 0 Interrupt disabled for TMS pin Default 1 Interrupt enabled for TMS pin in GPIO mode 5 TDI_INT_EN R W 0 TDI Interrupt Enable 0 Interrupt disabled for TDI pin Default 1 Interrupt enabled for TDI pin in GPIO mode 4 TDO_INT_EN R W 0 TDO Interrupt Enable 0 Interrupt disabled for TDO pin Default 1 Interrupt enabled for TDO pin in GPIO mode 3 FLT3_INT_EN R W 0 FAULT 3 Interrupt Enable 0 Interrup...

Page 289: ...ult 1 Interrupt generated on rising edge 5 TDI_INT_POL R W 0 TDI_INT_POL TDI Interrupt Polarity Select 0 Interrupt generated on falling edge Default 1 Interrupt generated on rising edge 4 TDO_INT_POL R W 0 TDO_INT_POL TDO Interrupt Polarity Select 0 Interrupt generated on falling edge Default 1 Interrupt generated on rising edge 3 FLT3_INT_POL R W 0 FLT3_INT_POL FAULT 3 Interrupt Polarity Select 0...

Page 290: ... Default 1 Interrupt pending 5 TDI_INT_PEND R W 0 TDI has caused an interrupt Writing a 1 to a bit will clear the interrupt flag 0 No Interrupt detected Default 1 Interrupt pending 4 TDO_INT_PEND R W 0 TDO has caused an interrupt Writing a 1 to a bit will clear the interrupt flag 0 No Interrupt detected Default 1 Interrupt pending 3 FLT3_INT_PEND R W 0 FAULT 3 has caused an interrupt Writing a 1 t...

Page 291: ... Register EXTINTDIR Address FFF7FA20 Figure 7 7 External Interrupt Direction Register EXTINTDIR 0 EXT_INT_DIR R W 0 LEGEND R W Read Write R Read only n value after reset Table 7 7 External Interrupt Direction Register EXTINTDIR Register Field Descriptions Bit Field Type Reset Description 0 EXT_INT_DIR R W 0 EXT INT Pin Configuration 0 EXT INT pin configured as an input pin Default 1 EXT INT pin co...

Page 292: ...rrupt Input Register EXTINTIN Address FFF7FA24 Figure 7 8 External Interrupt Input Register EXTINTIN 0 EXT_INT_EN R 0 LEGEND R W Read Write R Read only n value after reset Table 7 8 External Interrupt Input Register EXTINTIN Register Field Descriptions Bit Field Type Reset Description 0 EXT_INT_EN R 0 Input Value of EXT INT Pin 0 EXT INT pin driven low in GPIO mode 1 EXT INT pin driven high in GPI...

Page 293: ... Interrupt Output Register EXTINTOUT Address FFF7FA28 Figure 7 9 External Interrupt Output Register EXTINTOUT 0 EXT_INT_OUT R W 0 LEGEND R W Read Write R Read only n value after reset Table 7 9 External Interrupt Output Register EXTINTOUT Register Field Descriptions Bit Field Type Reset Description 0 EXT_INT_OUT R W 0 EXT INT Pin Output Value 0 EXT INT pin driven low Default 1 EXT INT pin driven h...

Page 294: ...Enable Register EXTINTENA Address FFF7FA34 Figure 7 10 External Interrupt Enable Register EXTINTENA 0 EXT_INT_EN R W 0 LEGEND R W Read Write R Read only n value after reset Table 7 10 External Interrupt Enable Register EXTINTENA Register Field Descriptions Bit Field Type Reset Description 0 EXT_INT_EN R W 0 EXT INT Interrupt Enable 0 Interrupt disabled for EXT INT pin Default 1 Interrupt enabled f...

Page 295: ...Register EXTTINTPOL Address FFF7FA38 Figure 7 11 External Interrupt Polarity Register EXTTINTPOL 0 EXT_INT_POL R W 0 LEGEND R W Read Write R Read only n value after reset Table 7 11 External Interrupt Polarity Register EXTTINTPOL Register Field Descriptions Bit Field Type Reset Description 0 EXT_INT_POL R W 0 EXT INT Interrupt Polarity Select 0 Interrupt generated on falling edge Default 1 Interru...

Page 296: ... EXT_INT_PEND R W 0 LEGEND R W Read Write R Read only n value after reset Table 7 12 External Interrupt Pending Register EXTINTPEND Register Field Descriptions Bit Field Type Reset Description 0 EXT_INT_PEND R W 0 EXT INT has caused an interrupt Writing a 1 to a bit will clear the interrupt flag 0 No Interrupt detected Default 1 Interrupt pending 7 13 References 1 UCD3138 ARM and Digital System Pr...

Page 297: ...urrent sources for excitation of PMBus addressing resistors Dual sample Hold for accurate power measurement Internal temperature sensor for temperature protection and monitoring The control module shown in Figure 8 1 contains the control and conversion logic for auto sequencing a series of conversions The sequencing is fully configurable for any combination of 16 possible ADC channels through an a...

Page 298: ...rors for the elements connected to the analog inputs of the converter Another problem is that all the sampling channels use the same S H capacitor in a sequence if the sampling speed is very high the charge remain on the S H capacitor of one conversion may affect the result of the next conversion channel Topic Page 8 1 ADC12 Input Impedance Model 299 8 2 ADC12 Impedance vs Sampling Frequency Data ...

Page 299: ...that selects the channel to be converted The second portion is the sample and hold circuit that is controlled by the control block of ADC12 There are several factors to be considered in the ADC input path the resistance of the CMOS switches and the capacitances associated with them the leakage resistance and the sample and hold capacitance The external components are also to be considered Figure 8...

Page 300: ...edance Test Setup The ADC12 channel input impedance vs sampling frequency data is shown in the Figure 8 5 At highest sampling frequency that UCD3138 ADC12 can the input impedance is around 300kohm at a sampling frequency of below 150kHz the channel impedance is above 3Mohm This data can be used as a general guideline of designing proper input R for the UCD3138 ADC12 or determine a proper operation...

Page 301: ...of the interested signal But it may not be obvious that the external C also plays the role in adjusting the source impedance and should be determined by the sampling frequency of the ADC as well Take the above experiment setup as an example if an external capacitor is added as shown in Figure 8 7 the external impedance becomes smaller Thus larger external capacitance helps reducing the charge time...

Page 302: ...ference Modes of operation for ADC12 conversion are highly configurable to suit the desired application 8 7 Conversion The ADC conversion is controlled by the ADC12 FSM that provides all the necessary control signals for the successive approximation register SAR ADC operation The binary search algorithm sampling time and bit timing are controlled by the state machine based on firmware configuratio...

Page 303: ... a sequence The start of the sequencer can be delayed from the receipt of an external trigger A counter within the ADC12 Control Finite State Machine will delay the start of the sequence based on a programmable delay configured by firmware After the delay the sequencer will start the conversions For example in order to initiate a sequence of measurements 128nS after the ADC_EXT_TRIG pin trips the ...

Page 304: ... auto limit monitoring the user must use these 6 ADC conversion slots for monitoring of those signals All 12 bits of conversion result are used for comparison The Digital Comparators provide 12 status bits for monitoring two from each ADC result comparison These status bits indicate whether the ADC result is higher or equal to the Limit High threshold or if it is lower or equal to the Limit Low th...

Page 305: ...t sample and 31 32 of previous average The averaging result register is stored immediately following the calculation of the moving average Upon receipt of the next ADC sample the ADC sample value and current moving average are used for calculation of the next moving average In addition 5 fractional bits from the moving average calculation are stored for use in the next moving average calculation T...

Page 306: ... Table 8 1 Temp Sensor Control Register TEMPSENCTRL Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R W 00 0000 0 TEMP_SENSE_ DIS R W 1 Temperature Sensor Disable 0 Enables Temperature Sensor 1 Disables Temperature Sensor Default CAUTION Writing into the reserved bits is NOT RECOMMENDED since it is likely to have an adverse effect on the normal operation of Temperature S...

Page 307: ...IAS_B_ENA 1 8 13 1 PMBus Control Register 3 PMBCTRL3 Address FFF7F620 Figure 8 12 PMBus Control Register 3 PMBCTRL3 20 19 18 17 16 15 CLK_LO_DIS IBIAS_B_EN IBIAS_A_EN SCL_DIR SCL_VALUE SCL_MODE R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 8 2 PMBus Control Register 3 PMBCTRL3 Register Field Descriptions Bit Field Type Reset Description 20 CLK_LO_D...

Page 308: ...as follows Dual sample and hold provides simultaneous sampling of two ADC inputs This is simply done by sampling and holding one channel exactly at the time a second channel is sampled for conversion and converting the sample and hold channel at a later event in the current measurement sequence Channels 2 1 and 0 are the ONLY channels with sample and hold capability These channels can be sampled s...

Page 309: ...EL_REF R W 0 11 ADC_ROUND R W 0 10 8 BYPASS_EN R W 111 Bypasses the dual sample and hold circuitry Bit 10 controls ADC Channel 2 Bit 9 controls ADC Channel 1 and Bit 8 controls ADC Channel 0 0 Enables the Dual Sample and Hold circuitry 1 Disables the Dual Sample and Hold circuitry Default 7 4 MAX_CONV R W 0000 8 15 Usage of Sample and Hold Circuitry for High Impedance Measurement In UCD3138 there ...

Page 310: ... Hold Circuitry in ADC12 Figure 8 16 shows the ADC12 dual sample and hold configuration table and operation principles Figure 8 16 ADC12 Dual Sample and Hold Configuration Here is an application example To use AD01 on high impedance node BYPASS_EN 5 select AD01 as dual sample and hold channel A buffer will be added to AD01 SEQ0 4 put AD04 on sequence 0 SEQ0_SH 1 enable AD04 to do dual sample and h...

Page 311: ...04 8 16 ADC Configuration Examples 8 16 1 Software Initiated Conversions The following example code demonstrates how to configure ADC12 to initiate a sequence of conversions triggered by software Requirement 10 conversions need to be sequenced during a single session with triggering done via firmware The required channels are as follows Conversions 09 10 02 02 02 04 04 04 12 and 14 Here the maximu...

Page 312: ...Regs ADCCTRL bit SINGLE_SWEEP 1 AdcRegs ADCCTRL bit ADC_EN 1 AdcRegs ADCSEQSEL0 bit SEQ0 3 Vout AD03 AdcRegs ADCSEQSEL0 bit SEQ1 2 Iout AD02 AdcRegs ADCSEQSEL0 bit SEQ2 4 Ipri AD04 AdcRegs ADCSEQSEL0 bit SEQ3 5 Ishare AD05 AdcRegs ADCSEQSEL1 bit SEQ4 6 Vin voltage sensing AdcRegs ADCSEQSEL1 bit SEQ5 7 Copper Temp AD12 AdcRegs ADCSEQSEL1 bit SEQ6 8 Ext Temp AD08 AdcRegs ADCAVGCTRL bit AVG0_CONFIG 2...

Page 313: ...ification of end of conversion is not really required pragma INTERRUPT standard_interrupt IRQ void standard_interrupt void poll_adc 8 16 3 Auto Triggered Conversions A conversion sequence may also be initiated via external triggers without firmware initiation Sources of external triggering include the DPWM outputs the analog comparators and the ADC_EXT_TRIG pin The sequencer operation is defined b...

Page 314: ... values of SEQ00 I1 SEQ01 I2 SEQ02 I3 SEQ03 I4 SEQ04 I5 and SEQ05 I6 are performed At the end of the auto conversion session the ADC result registers have the following values Buffer Registers ADC Conversion Result RESULT 00 I1 RESULT 01 I2 RESULT 02 I3 RESULT 03 I4 RESULT 04 I5 RESULT 05 I6 Note at this point the sequencer remains at its current state waiting for another trigger 8 16 5 Start Stop...

Page 315: ... set to be the fifth sixth and the seventh SEQ4 to SEQ6 respectively in the measurement sequence AdcRegs ADCCTRL bit SW_START 1 Means the ADC is instructed to start a new conversion sequence AdcRegs ADCCTRL bit ADC_INT_EN 1 Means enable interrupt at local ADC level CimRegs REQMASK bit REQMASK_ADC_CONV 1 Means Enable ADC interrupt at CPU level if AdcRegs ADCSTAT bit ADC_INT 1 Means if ADC measureme...

Page 316: ...V SINGLE_ SWEEP SW_START ADC_INT_EN ADC_EN R W 0000 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 8 5 ADC Control Register ADCCTRL Register Field Descriptions Bit Field Type Reset Description 31 24 EXT_TRIG_DLY R W 0000 0000 8 bit External ADC Trigger Delay configuration LSB bit resolution equals period of ADC Clock High Frequency Oscillator Frequency divided ...

Page 317: ...01 744KS s 000 267KS s Default 12 ADC_SEL_REF R W 0 ADC Voltage Reference Select 0 Selects Internal ADC voltage reference Default 1 Selects AVDD as ADC voltage reference 11 ADC_ROUND R W 0 Enables rounding of ADC Result to 10 bits 0 ADC Results are not rounded Default 1 ADC Results are rounded to 10 most significant bits 10 8 BYPASS_EN R W 111 Bypasses the dual sample and hold circuitry Bit 10 con...

Page 318: ...ue after reset Table 8 6 ADC Status Register ADCSTAT Register Field Descriptions Bit Field Type Reset Description 6 3 CURRENT_CH R 0 Register shows the currently converting channel 2 ADC_EXT_TRIG_ VAL R 0 ADC_EXT_TRIG pin value 0 ADC_EXT_TRIG pin driven low 1 ADC_EXT_TRIG pin driven high 1 ADC_INT_RAW R 0 End of conversion interrupt flag raw version 0 No End of conversion interrupt detected 1 End ...

Page 319: ...egister Field Descriptions Bit Field Type Reset Description 9 6 TEST_CH_SEL R W 0000 Selects channel to convert in ADC Test Mode 0 Channel 0 selected Default 1 Channel 1 selected 2 Channel 2 selected 3 Channel 3 selected 4 Channel 4 selected 5 Channel 5 selected 6 Channel 6 selected 7 Channel 7 selected 8 Channel 8 selected 9 Channel 9 selected 10 Channel 10 selected 11 Channel 11 selected 12 Chan...

Page 320: ...cted for Dual Sampling 27 24 SEQ3 R W 0000 Channel to be converted fourth 0000 Channel 0 selected Default 0001 Channel 1 selected 1111 Channel 15 selected 23 21 Reserved R 000 20 SEQ2_SH R W 0 Dual channel sequence select 0 Not selected for Dual Sampling Default 1 Selected for Dual Sampling 19 16 SEQ2 R W 0000 Channel to be converted third 0000 Channel 0 selected Default 0001 Channel 1 selected 11...

Page 321: ...ted for Dual Sampling 27 24 SEQ7 R W 0000 Channel to be converted eighth 0000 Channel 0 selected Default 0001 Channel 1 selected 1111 Channel 15 selected 23 21 Reserved R 000 20 SEQ6_SH R W 0 Dual channel sequence select 0 Not selected for Dual Sampling Default 1 Selected for Dual Sampling 19 16 SEQ6 R W 0000 Channel to be converted seventh 0000 Channel 0 selected Default 0001 Channel 1 selected 1...

Page 322: ...cted for Dual Sampling 27 24 SEQ11 R W 0000 Channel to be converted twelfth 0000 Channel 0 selected Default 0001 Channel 1 selected 1111 Channel 15 selected 23 21 Reserved R 000 20 SEQ10_SH R W 0 Dual channel sequence select 0 Not selected for Dual Sampling Default 1 Selected for Dual Sampling 19 16 SEQ10 R W 0000 Channel to be converted eleventh 0000 Channel 0 selected Default 0001 Channel 1 sele...

Page 323: ...r Dual Sampling 27 24 SEQ15 R W 0000 Channel to be converted sixteenth 0000 Channel 0 selected Default 0001 Channel 1 selected 1111 Channel 15 selected 23 21 Reserved R 000 20 SEQ14_SH R W 0 Dual channel sequence select 0 Not selected for Dual Sampling Default 1 Selected for Dual Sampling 19 16 SEQ14 R W 0000 Channel to be converted fifteenth 0000 Channel 0 selected Default 0001 Channel 1 selected...

Page 324: ...lt Register 6 Address 00040038 ADC Result Register 7 Address 0004003C ADC Result Register 8 Address 00040040 ADC Result Register 9 Address 00040044 ADC Result Register 10 Address 00040048 ADC Result Register 11 Address 0004004C ADC Result Register 12 Address 00040050 ADC Result Register 13 Address 00040054 ADC Result Register 14 Address 00040058 ADC Result Register 15 Figure 8 26 ADC Result Regist...

Page 325: ... 1 Address 00040064 ADC Averaged Result Register 2 Address 00040068 ADC Averaged Result Register 3 Address 0004006C ADC Averaged Result Register 4 Address 00040070 ADC Averaged Result Register 5 Figure 8 27 ADC Averaged Result Registers 0 5 ADCAVGRESULTx x 0 15 11 0 RESULT R 0 LEGEND R W Read Write R Read only n value after reset Table 8 13 ADC Averaged Result Registers 0 5 ADCAVGRESULTx x 0 15 Re...

Page 326: ...ER_LIMIT R W 1111 1111 1111 R 0000 R W 0000 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 8 14 ADC Digital Compare Limits Register 0 5 ADCCOMPLIMx x 0 5 Register Field Descriptions Bit Field Type Reset Description 27 16 UPPER_LIMIT R W 1111 1111 1111 Configures the upper limit value If the ADC conversion selected is equal or greater than the limit the Digital Compare Interr...

Page 327: ...ult below lower limit 25 COMP4_UP_INT_ EN R W 0 Digital Comparator 4 Upper Limit Interrupt Enable 0 Interrupt generation disabled on result above upper limit Default 1 Interrupt generation enabled on result above upper limit 24 COMP4_LO_INT_ EN R W 0 Digital Comparator 4 Lower Limit Interrupt Enable 0 Interrupt generation disabled on result below lower limit Default 1 Interrupt generation enabled ...

Page 328: ...or comparison 11 COMP3_DATA_S EL R W 0 Digital Comparator 3 Data Select 0 Raw ADC Result 3 used for comparison Default 1 Averaged ADC Result 3 used for comparison 10 COMP2_DATA_S EL R W 0 Digital Comparator 2 Data Select 0 Raw ADC Result 2 used for comparison Default 1 Averaged ADC Result 2 used for comparison 9 COMP1_DATA_S EL R W 0 Digital Comparator 1 Data Select 0 Raw ADC Result 1 used for com...

Page 329: ...y n value after reset Table 8 16 ADC Digital Compare Results Register ADCCOMPRESULT Register Field Descriptions Bit Field Type Reset Description 27 DCOMP5_UP_RAW R 0 Digital Comparator 5 Upper Limit Raw Result 0 Limit not exceeded 1 Limit exceeded 26 DCOMP5_LO_RAW R 0 Digital Comparator 5 Lower Limit Raw Result 0 Limit not exceeded 1 Limit exceeded 25 DCOMP4_UP_RAW R 0 Digital Comparator 4 Upper L...

Page 330: ...read 0 Limit not exceeded 1 Limit exceeded 8 DCOMP4_LO_INT R 0 Digital Comparator 4 Lower Limit Interrupt Result cleared on read 0 Limit not exceeded 1 Limit exceeded 7 DCOMP3_UP_INT R 0 Digital Comparator 3 Upper Limit Interrupt Result cleared on read 0 Limit not exceeded 1 Limit exceeded 6 DCOMP3_LO_INT R 0 Digital Comparator 3 Lower Limit Interrupt Result cleared on read 0 Limit not exceeded 1 ...

Page 331: ...Moving average of 16 samples 3 Moving average of 32 samples 20 AVG5_EN R W 0 ADC Averaging Module 5 Enable 0 ADC Averaging Disabled Default 1 ADC Averaging Enabled 19 Reserved R 0 18 17 AVG4_CONFIG R W 00 ADC Averaging Module 4 Configuration 0 Moving average of 4 samples Default 1 Moving average of 8 samples 2 Moving average of 16 samples 3 Moving average of 32 samples 16 AVG4_EN R W 0 ADC Averagi...

Page 332: ...figuration 0 Moving average of 4 samples Default 1 Moving average of 8 samples 2 Moving average of 16 samples 3 Moving average of 32 samples 4 AVG1_EN R W 0 ADC Averaging Module 1 Enable 0 ADC Averaging Disabled Default 1 ADC Averaging Enabled 3 Reserved R 0 2 1 AVG0_CONFIG R W 00 ADC Averaging Module 0 Configuration 0 Moving average of 4 samples Default 1 Moving average of 8 samples 2 Moving aver...

Page 333: ... blocks These controls are usually used at the time of trimming at IC manufacturing therefore this document will not cover these trim controls Please note that despite the name Miscellaneous Analog Control the MAC module does not only control analog functions All the MAC registers and peripherals are available in the UCD3138RGC 64 pin version The UCD3138RHA 40 pin version device may have reduced r...

Page 334: ...ase by an interrupt service routine Please refer to Section 3 6 of UCD3138 device datasheet for more information about specific Brownout threshold levels 9 3 Temperature Sensor Control Temperature sensor control register provides internal temperature sensor enabling and trimming capabilities The internal temperature sensor is disabled as default 9 4 I O Mux Control In different package versions of...

Page 335: ... 2K 25 Resistor support no more than 1 mA ESDRES 250 25 ESD resistor Iconst 250µA 2 Use in PWM output current Table 9 2 Current Sharing Mode CSCTRL bit TEST_MODE Switch θ1 Switch θ2 Digital PWM Tri state or Slave mode 0 OFF OFF OFF PWM average current Bus 1 ON OFF ACTIVE Analog average current Bus or Master mode 3 OFF ON OFF The period and the duty of 8 bit PWM current source and the state of the ...

Page 336: ...trol Power Disable Control register provides control bits that can enable or disable arrival of clock to several peripherals such as PCM CPCC digital filters front ends DPWMs UARTs ADC 12 and more All these controls are enabled as default If a specific peripheral is not used in a specific application the clock gate can be disabled in order to block the propagation of clock signal to that periphera...

Page 337: ... INT_EN COMP_EN R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 9 4 Brownout Register BROWNOUT Register Field Descriptions Bit Field Type Reset Description 2 INT R 0 Brownout Interrupt Status 0 No Brownout Condition observed 1 Brownout Condition observed 1 INT_EN R W 0 Brownout Interrupt Enable 0 Brownout Interrupt disabled Default 1 Brownout Interrupt enabled 0 COMP_EN...

Page 338: ...value after reset Table 9 5 Temp Sensor Control Register TEMPSENCTRL Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R W 00 0000 Temperature Sensor Disable 0 Enables Temperature Sensor 1 Disables Temperature Sensor Default 0 TEMP_SENSE _DIS R W 0 CAUTION Writing into the reserved bits is NOT RECOMMENDED since it is likely to have an adverse effect on the normal operation...

Page 339: ... Read only n value after reset Table 9 6 Bits 9 8 EXT_TRIG_MUX_SEL EXT_TRIG Pin Mux Select I O Pin 0 1 2 3 EXT TRIG EXT TRIG TCAP SYNC PWM 0 Table 9 7 Bits 7 6 JTAG_CLK_MUX_SEL TCK Pin Mux Select I O Pin 0 1 2 3 TCK TCK TCAP SYNC PWM 0 Table 9 8 Bits 5 4 JTAG_DATA_MUX_SEL TDO TDI Pin Mux Select I O Pin 0 1 2 3 TDO TDO SCI_TX 0 ALERT FAULT 0 TDI TDI SCI_RX 0 CONTROL FAULT 1 Table 9 9 Bits 3 2 SYNC_...

Page 340: ...l Register CSCTRL Register Field Descriptions Bit Field Type Reset Description 23 16 DPWM_DUTY R W 0000 0000 Configures Pulse Width Duty Cycle for DPWM output to Current Sharing circuit Resolution of LSB equals period of MCLK clock 32 ns 15 8 DPWM_PERIOD R W 0000 0000 Configures Period for DPWM output to Current Sharing circuit Output period equals DPWM_PERIOD 1 LSB resolution Resolution of LSB eq...

Page 341: ...EMPREF Address FFF7F03C Figure 9 9 Temperature Reference Register TEMPREF 11 0 TEMP_REF R W 0000 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 9 14 Temperature Reference Register TEMPREF Register Field Descriptions Bit Field Type Reset Description 11 0 TEMP_REF R W 0000 0000 0000 Reference measurement taken during factory trim ADC12 measurement of the internal temperature s...

Page 342: ...wer Constant Current Module 1 Enables clocks to Constant Power Constant Current Module Default 15 FILTER2_CLK_EN R W 1 Clock Enable for Filter 2 Module 0 Disables clocks to Filter 2 Module 1 Enables clocks to Filter 2 Module Default 14 FILTER1_CLK_EN R W 1 Clock Enable for Filter 1 Module 0 Disables clocks to Filter 1 Module 1 Enables clocks to Filter 1 Module Default 13 FILTER0_CLK_EN R W 1 Clock...

Page 343: ...ut or output pin GPIO The only pins that can not be configured as GPIO pins are the Supply pins Ground pins ADC 12 analog input pins EADC analog input pins and RESET pin All digital pins with the exception of RESET pin can be configured as GPIOs There are two ways to configure and use the digital pins as GPIO pins 1 Through the centralized Global I O control registers 2 Through the distributed con...

Page 344: ...end to clarify and compare the utilization of local peripheral controls versus the use of centralized Global I O controls Example 1 Setting a DPWM3B pin as a general purpose output GPO and set the output high The following examples demonstrate two alternatives Example 1 1 configuration through DPWM registers Dpwm3Regs DPWMCTRL1 bit GPIO_A_ENA 1 Configure DPWM3A as a GPIO Dpwm3Regs DPWMCTRL1 bit PW...

Page 345: ...Global I O bits Examples Configure the ADC_EXT_TRIG TMR_PWM1 FAULT2 FAULT3 and SYNC pins as GPIO pins MiscAnalogRegs GLBIOEN all ADC_EXT_TRIG_GLBIO_BIT_MASK TMR_PWM1 FAULT2_GLBIO_BIT_MASK FAULT3_GLBIO_BIT_MASK SYNC_GLBIO_BIT_MASK Set Both FAULT2 and FAULT3 pins high MiscAnalogRegs GLBIOOE all FAULT2_GLBIO_BIT_MASK FAULT3_GLBIO_BIT_MASK Clear Both FAULT2 and FAULT3 pins set to low MiscAnalogRegs GL...

Page 346: ...eld Descriptions Bit Field Type Reset Description 29 0 GLOBAL_IO_EN R W 00 0000 0000 0000 0000 0000 0000 0000 This register enables the global control of digital I O pins 0 Control of IO is done by the functional block assigned to the IO Default 1 Control of IO is done by Global IO registers Bit assignment is done by this table BIT PIN_NAME BIT PIN_NAME 29 FAULT 3 14 CONTROL 28 ADC_EXT_TRIG 13 ALE...

Page 347: ...l I O OE Register GLBIOOE Register Field Descriptions Bit Field Type Reset Description 29 0 GLOBAL_IO_OE R W 00 0000 0000 0000 0000 0000 0000 0000 This register controls the output enable signals for all digital I O pins 0 Input Default 1 Output Bit assignment is done by this table BIT PIN_NAME BIT PIN_NAME 29 FAULT 3 14 CONTROL 28 ADC_EXT_TRIG 13 ALERT 27 TCK 12 EXT_INT 26 TDO 11 FAULT 2 25 TMS 1...

Page 348: ...ster GLBIOOD Register Field Descriptions Bit Field Type Reset Description 29 0 GLOBAL_IO_OD R W 00 0000 0000 0000 0000 0000 0000 0000 This register controls if the global IO is configured as an open drain This bit multiplexes the GLOBAL_IO_VALUE register to the OE signals 0 Normal I O Default 1 Open Drain Bit assignment is done by this table BIT PIN_NAME BIT PIN_NAME 29 FAULT 3 14 CONTROL 28 ADC_E...

Page 349: ...criptions Bit Field Type Reset Description 29 0 GLOBAL_IO_ VALUE R W 00 0000 0000 0000 0000 0000 0000 0000 This register set the output value of the digital I O pins when configured as outputs 0 Digital I O pin configured as low in output mode Default 1 Digital I O pin configured as high in output mode Bit assignment is done by this table BIT PIN_NAME BIT PIN_NAME 29 FAULT 3 14 CONTROL 28 ADC_EXT_...

Page 350: ...d Register GLBIOREAD Register Field Descriptions Bit Field Type Reset Description 29 0 GLOBAL_IO_ READ R 0 This register provides the value on these signals after I O muxing 0 Digital I O pin low Default 1 Digital I O pin high Bit assignment is done by this table BIT PIN_NAME BIT PIN_NAME 29 FAULT 3 14 CONTROL 28 ADC_EXT_TRIG 13 ALERT 27 TCK 12 EXT_INT 26 TDO 11 FAULT 2 25 TMS 10 FAULT 1 24 TDI 9 ...

Page 351: ...HERM_TRIM HFO_E NABLE R W 011 1000 R W 10 R W 1 R W 0 R W 011 R W 1 LEGEND R W Read Write R Read only n value after reset Table 9 21 Clock Trim Register CLKTRIM For Factory Test Use Only Except HFO_LN_FILTER_EN Register Field Descriptions Bit Field Type Reset Description 14 8 HFO_CLK_TRIM R W 011 1000 High Frequency Oscillator Clock Trim Bits Register will be programmed during test and should not ...

Page 352: ...itration Automatic Clock Low Timeout detection in hardware Address Mask permits automatic acknowledge of multiple addresses Flexible Supports polling and interrupt driven firmware Can be configured to automatically acknowledge 1 2 or 3 bytes of data at a time on the fly Auto or manual acknowledge of Address and Command bytes Supports 100 and 400 kHz Access to state of each PMBus Pin Additional fea...

Page 353: ... as possible PMBCTRL1 All zeroes this is the default so no write is necessary PMBCTRL2 Several bits need to be set RX_BYTE_ACK_CNT 3 this means up to 3 bytes will be auto acknowledged it is the default state of these bits after reset PEC_ENA 1 this enables the automatic PEC calculation logic this is not the default state SLAVE_MASK 0x7F This makes the interface auto acknowledge only one address th...

Page 354: ...A UCD3138128 and UCD3138128A can automatically acknowledge a second address To use this Write the address to the SLAVE_ADDR_2 bitfield in PMBCTRL2 Set the SLAVE_ADDR_2_EN bit in PMBCTRL2 These fields are only available on the 128 and 128A devices 10 2 4 2 Clock High Timeout Detection The UCD3138 and UCD3138064 devices have bits called CLK_HIGH_DETECT in PBINTM and CLK_HIGH_TIMEOUT in PMBST but the...

Page 355: ... will be set and the PMBus hardware will go to an idle state and wait for a new message To enable an interrupt clear the bit in PMBINTM The 50 msec time is not an official PMBus specification but it is a useful way to determine if the bus clock is stuck high With the hardware timeout detection it is not necessary to use any firmware to detect timeout 10 3 PMBus Slave Mode Command Examples The logi...

Page 356: ...e clear on read status bits It will also clear any interrupts caused by those bits The firmware will determine which message type is present from the PMBST bits 3 Next the firmware needs to get the data from the RXBUF register Then it needs to write a 1 to the ACK register This tells the PMBus hardware that it can accept new data In this case the ACK is only used internally to tell the interface t...

Page 357: ...evised April 2016 Submit Documentation Feedback Copyright 2016 Texas Instruments Incorporated PMBus Interface I2C Interface 10 3 2 Other Simple Writes with Auto Acknowledge Writes with an address and up to 3 bytes of data command PEC will be handled essentially the same way as the one with a single byte For simplicity the ACK and clock stretching sequence will be left off these drawings Figure 10 ...

Page 358: ...ce is the number put in RD_BYTE_COUNT and the value put in PEC_VALID The command byte any data bytes and the PEC all are included in the RD_BYTE_COUNT 10 3 3 Quick Command Write The Quick Command has only the address byte with the R W bit cleared to indicate a write It is just the same as the messages above except the DATA_RDY and RD_BYTE_COUNT bits will not be set Since there is no data only the ...

Page 359: ... RXBUF and writes a 1 to the ACK bit This turns off the clock stretch The delay between write to ACK and disable of clock stretch is tACKWRITE Reading from PMBST clears the DATA_RDY bit and the RD_BYTE_COUNT bits 3 On the falling edge of PMBUS_CLK indicating the STOP signal the EOM bit is set and the PEC_VALID bit is set or cleared to indicate if the last byte was a valid PEC The timing after the ...

Page 360: ...e assumes that RX_BYTE_ACK_CNT is set to the maximum value of 3 meaning that 3 bytes will be ACKed automatically If it is set to 2 for example the sequence will repeat every 3 bytes instead of every 4 If it is set to 0 every byte will need to be ACKed the same way as shown above for every 4 bytes Using less than 4 bytes in the RX_BYTE_ACK_CNT is only recommended if the requirement is for NACK of i...

Page 361: ...anual ACK Command Manual command timing is actually exactly the same as the timing for a byte when the RXBUF needs to be read 1 tDRDY after the falling clock for the last bit of the command DATA_RDY is set and 1 is put into RD_BYTE_COUNT 2 The firmware reads PMBST and then reads the command from RXBUF 3 The firmware writes a 1 or a 0 to the ACK register depending on whether the command is accepted...

Page 362: ...o clock stretching will occur 4 As soon as the data starts being transmitted the TXBUF is transferred to the shift register 5 The EOM bit will be set tEOM ns after the falling edge of the data line indicating the stop signal 6 The firmware needs to read the PMBST register which will clear the EOM bit 7 Then the firmware needs to write to the ACK register This is just an internal ACK to tell the in...

Page 363: ...d of More than 4 Bytes with Full Automation After the 4 byte TXBUF is emptied there is a sequence for reloading it Here is the diagram Figure 10 12 Simple Read of 5 Bytes with Full Automation 1 DATA_REQUEST is set tDREQ1 nanoseconds after the falling edge of the clock for the last bit of the address 2 The firmware reads from PMBST clearing the DATA_REQUEST bit Since 4 bytes are being sent out the ...

Page 364: ...tinues with TXBUF reloads every 4 bytes until the end of the message is reached If code is being ported from an processor limited to a 1 byte TXBUF it is possible to always write only 1 byte to TXBUF and to keep TX _COUNT always a 1 This will significantly increase overhead because the data request write to TXBUF sequence will occur on every byte instead of every 4 10 3 11 Quick Command Read New P...

Page 365: ...ll be cleared tTXWRITE ns after the write to TXBUF If the firmware is fast enough no clock stretch will occur 6 Once the ACK is over the ACK bit will be cleared and the TXBUF will be moved into the shift register for transmission After the manual slave ACK the rest of the read will continue as described in the sequences above 10 3 13 Write Read with Repeated Start Both PMBus and I2C provide for a ...

Page 366: ...same as a standard write sequence except that they end with a repeated start rather than an EOM 10 3 14 Automatic PEC Addition For PMBus commands the UCD also provides for automatic addition of a PEC byte at the end When writing the last bytes in the message to the TXBUF first set the TX_PEC bit The interface will automatically send out the number of bytes in TXBUF and then add a PEC byte at the e...

Page 367: ...clock stretching tX needs to be smaller than the clock low time for the PMBus I2C clock speed Since tDREQ1 tACKWRITE 1 076 µsec maximum it s possible to just subtract this number from the minimum clock low time for the data rate At 100 KHz clock low minimum is 4 7 µsec giving about 3 7 µsec for firmware which should be attainable with an optimized interrupt Obviously the minimum clock low time of ...

Page 368: ...l pull the ALERT pin low and enable the ALERT response from the hardware If MAN_SLAVE_ACK is not set the hardware will automatically acknowledge the special ALERT address and will automatically to the arbitration with the device address If the UCD wins the arbitration it will automatically release the ALERT line and clear the ALERT_EN bit In manual address acknowledge mode MAN_SLAVE_ACK is set the...

Page 369: ...nterface I2C Interface 10 5 PMBus Slave Mode Low Level Timing These diagrams give the low level timing for the PMBus logic They show the timing between events on the PMBus pins and PMBus register changes For each timing parameter only one case is shown Note that the same timing parameter may occur in different places in a PMBus message Some of the timing diagrams show a clock stretch These are opt...

Page 370: ...a Byte A 7 8 Write to TXBUF Stretch tDREQ3 tTXBWRITE PMBus Slave Mode Low Level Timing www ti com 370 SNIU028A February 2016 Revised April 2016 Submit Documentation Feedback Copyright 2016 Texas Instruments Incorporated PMBus Interface I2C Interface Figure 10 19 Read Byte Timing Note Stretch is optional depending on firmware timing Figure 10 20 Write Byte Timing Figure 10 21 Write Byte Stop Timing...

Page 371: ... as PEC VALID and RD_BYTE_COUNT loaded with correct value 427 538 ns Table 10 3 PMBus I2C edge which triggers change Bit Field Changed Min ns Max ns SCL rise or fall SCL_RAW set or clear 244 336 SDA rise or fall SDA_RAW set or clear 244 336 CONTROL rise or fall CONTROL_RA W set or clear 244 336 ALERT rise or fall ALERT_RAW set or clear 244 336 CONTROL edge specified by CNTL_INT_EDGE CONTROL_EDG E ...

Page 372: ... forces the PMBus Interface to append a PEC byte onto the end of the message The firmware is not required to calculate the PEC value or account for the PEC byte when entering the number of bytes in the message The Byte Count bits Bits 15 8 within the Master Control Register configures the number of data bytes within the outgoing message The firmware is required to program the byte count at the sta...

Page 373: ...n onto the PMBus 10 7 2 Send Byte Figure 10 23 Send Byte w o PEC Byte Figure 10 24 Send Byte with PEC Byte A Send Byte message consists of the device address a single data byte and an optional PEC byte To initiate a Send Byte message the data byte to be transmitted to the slave is loaded into bits 7 0 of the Transmit Data Register The Master Control Register is configured with the device address T...

Page 374: ...4 Write Byte Word Figure 10 27 Write Byte w o PEC Byte Figure 10 28 Write Byte with PEC Byte Figure 10 29 Write Word w o PEC Byte Figure 10 30 Write Word with PEC Byte The Write Byte and Write Word messages consist of a device address a command byte transmitted data bytes and an optional PEC byte Write Byte messages include a single byte while the Write Word messages support transmission of 2 byte...

Page 375: ...configured to receive 1 or 2 bytes the CMD_EN bit is set and the PEC_EN is configured to expect or not expect a PEC byte appended to the message The PMBus Interface will automatically terminate the message after the expected number of bytes is received from the slave or if the slave does not properly acknowledge any portion of the message In addition to programming the Master Control Register the ...

Page 376: ...plete the Write Word portion of the Process Call the Transmit Data Register is loaded with the command byte in Bits 7 0 and the data bytes are loaded into Bits 23 8 of the register After programming the Master Control Register the PMBus Interface initiates the Process Call Message on the PMBus The firmware can wait for an End of Message interrupt from the interface to determine the validity of the...

Page 377: ...of data bytes excluding the command byte and the first data byte that contains the block length The PMBus Interface will automatically insert the block length into the message if the number of data bytes specified by the firmware exceeds 2 The initial write data is loaded into the Transmit Data Register With bits 7 0 representing the command byte the remaining 3 bytes represent the first three dat...

Page 378: ...essage on the PMBus the Master Control Register is programmed with the block length in the Byte Count bits This count excludes the command byte any slave address and the block length bytes in the message The command byte to be transmitted to the Slave is written into bits 7 0 of the Transmit Data Register prior to the programming of the Master Control Register After configuring the Master Control ...

Page 379: ...rite portion of the message In addition the PRC_CALL bit within the Master Control Register must be enabled Upon completion of the Block Write part of the message the PMBus Interface will automatically issue a Repeated Start condition on the PMBus and start transmission of the Block Read portion of the message Operation of the PMBus Interface after the Repeated Start condition is the same as would...

Page 380: ...Byte A Byte 0 A PEC A P S Device Addr Wr A Command Byte A Ext Command Byte A Byte 0 A P Master Mode Operation Reference www ti com 380 SNIU028A February 2016 Revised April 2016 Submit Documentation Feedback Copyright 2016 Texas Instruments Incorporated PMBus Interface I2C Interface 10 7 11 Extended Command Write Byte Word Read Byte Word Figure 10 44 Extended Command Write Byte w o PEC Byte Figure ...

Page 381: ...ecuted concurrently To initiate a Group Command the GRP_CMD bit within the Master Control Register must be set when programming the slave address for the first device in the message The rest of the message is processed as a write byte word message At the conclusion of the first part of the Group Command message the firmware programs the next device address in the Master Control Register The PMBus ...

Page 382: ... Register 1 PMBCTRL1 Address FFF7F600 Figure 10 53 PMBUS Control Register 1 PMBCTRL1 20 19 18 17 16 PRC_CALL GRP_CMD PEC_ENA EXT_CMD CMD_ENA R W 0 R W 0 R W 0 R W 0 R W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BYTE_COUNT SLAVE_ADDR RW R W 0000 0000 R W 000 0000 R W 0 LEGEND R W Read Write R Read only n value after reset Table 10 5 PMBUS Control Register 1 PMBCTRL1 Register Field Descriptions Bit Fi...

Page 383: ...l Register 1 PMBCTRL1 Register Field Descriptions continued Bit Field Type Reset Description 7 1 SLAVE_ADDR R W 000 0000 Specifies the address of the slave to which the current message is directed towards 0 RW R W 0 Indicates if current Master initiated message is read operation or write operation 0 Message is a write transaction data from Master to Slave Default 1 Message is a read transaction da...

Page 384: ...YTE1 BYTE0 R W 0000 0000 R W 0000 0000 R W 0000 0000 R W 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 10 6 PMBus Transmit Data Buffer PMBTXBUF Register Field Descriptions Bit Field Type Reset Description 31 24 BYTE3 R W 0000 0000 Last data byte transmitted from Transmit Data Buffer 23 16 BYTE2 R W 0000 0000 Third data byte transmitted from Transmit Data Buffer 15 8 BYTE1 R...

Page 385: ...Register PMBRXBUF 31 24 23 16 15 8 7 0 BYTE3 BYTE2 BYTE1 BYTE0 R 0 R 0 R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 10 7 PMBus Receive Data Register PMBRXBUF Register Field Descriptions Bit Field Type Reset Description 31 24 BYTE3 R 0 Last data byte received in Receive Data Buffer 23 16 BYTE2 R 0 Third data byte received in Receive Data Buffer 15 8 BYTE1 R 0 Second data byte...

Page 386: ...e Register PMBACK Address FFF7F60C Figure 10 56 PMBus Acknowledge Register PMBACK 0 ACK R W 0 LEGEND R W Read Write R Read only n value after reset Table 10 8 PMBus Acknowledge Register PMBACK Register Field Descriptions Bit Field Type Reset Description 0 ACL R W 0 Allows firmware to acknowledge or not acknowledge received data 0 NACK received data Default 1 Acknowledge received data bit clears up...

Page 387: ...logic level low 1 PMBus data pin observed at logic level high 19 CONTROL_RAW R 0 Control Pin Real Time Status 0 Control pin observed at logic level low 1 Control pin observed at logic level high 18 ALERT_RAW R 0 Alert Pin Real Time Status 0 Alert pin observed at logic level low 1 Alert pin observed at logic level high 17 CONTROL_EDGE R 0 Control Edge Detection Status 0 Control pin has not transiti...

Page 388: ...NACK R 0 Not Acknowledge Flag Status 0 Data transmitted has been accepted by receiver 1 Receiver has not accepted transmitted data 5 EOM R 0 End of Message Indicator 0 Message still in progress or PMBus in idle state 1 End of current message detected 4 DATA_REQUEST R 0 Data Request Flag 0 No data needed by PMBus Interface 1 PMBus Interface request additional data PMBus clock stretching enabled to ...

Page 389: ...ag 1 Disables interrupt generation upon assertion of Control flag Default 6 ALERT R W 1 Alert Detection Interrupt Mask 0 Generates interrupt upon assertion of Alert flag 1 Disables interrupt generation upon assertion of Alert flag Default 5 EOM R W 1 End of Message Interrupt Mask 0 Generates interrupt upon assertion of End of Message flag 1 Disables interrupt generation upon assertion of End of Me...

Page 390: ...e received by slave Firmware is required to manually acknowledge every received byte 01 2 bytes received by slave Hardware automatically acknowledges the first received byte Firmware is required to manually acknowledge after the second received byte 10 3 bytes received by slave Hardware automatically acknowledges the first 2 received bytes Firmware is required to manually acknowledge after the thi...

Page 391: ...tch Writing a 0 to all bits in the mask enables the PMBus Interface to acknowledge any device address Upon power up the slave mask defaults to 7Fh indicating the slave will only acknowledge the address programmed into the Slave Address Bits 6 0 7 MAN_SLAVE _ACK R W 0 Manual Slave Address Acknowledgement Mode 0 Slave automatically acknowledges device address specified in SLAVE_ADDR Bits 6 0 Default...

Page 392: ... Address FFF7F61C Figure 10 60 PMBus Hold Slave Address Register PMBHSA 7 6 5 4 3 2 1 0 SLAVE_ADDR SLAVE_RW R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 10 12 PMBus Hold Slave Address Register PMBHSA Register Field Descriptions Bit Field Type Reset Description 7 1 SLAVE_ADDR R 0 Stored device address acknowledged by the slave 0 SLAVE_RW R 0 Stored R W bit from address acknow...

Page 393: ... automatic insertion of number of bytes in block writes in master mode Only available on UCD3138A64 and UCD3138128 A and non A versions 23 CLK_HI_DIS R W 1 Clock High Timeout Disable 0 Clock High Timeout Enabled 1 Clock High Timeout Disabled Default Only available on UCD3138A64 and UCD3138128 A and non A versions 23 CLK_HI_EN R W 0 Clock High Timeout Enable 0 Clock High Timeout Disabled Default 1 ...

Page 394: ...ALUE R W 0 Configures output value of Control pin in GPIO Mode 0 Control pin driven low in GPIO Mode Default 1 Control pin driven high in GPIO Mode 9 CNTL_MODE R W 0 Configures mode of Control pin 0 Control pin configured in functional mode Default 1 Control pin configured as GPIO 8 ALERT_DIR R W 0 Configures direction of Alert pin in GPIO mode 0 Control pin configured as output Default 1 Control ...

Page 395: ...ht 2016 Texas Instruments Incorporated PMBus Interface I2C Interface Table 10 13 PMBus Control Register 3 PMBCTRL3 Register Field Descriptions continued Bit Field Type Reset Description 0 RESET R W 0 PMBus Interface Synchronous Reset 0 No reset of internal state machines Default 1 Control state machines are reset to initial states ...

Page 396: ...imer with Capture and Compare 397 11 2 T24 Clock Source Prescaler and Counter 397 11 3 T24 Capture Block 398 11 4 T24 Compare Blocks 399 11 5 T24 Interrupts 399 11 6 T16PWMx 16 Bit PWM Timers 399 11 7 T16PWMx Summary 399 11 8 T16PWMx Prescaler and Counter 400 11 9 T16PWMx Compare Blocks 400 11 10 T16 Shadow Bit 401 11 11 T16 Interrupts 401 11 12 Using the T16 for a Timer Interrupt 402 11 13 Using ...

Page 397: ...ce firmware The first term TimerRegs refers to the Timer Register block The second term T24CNTCTRL refers to the specific register within that block Bit refers to the bit map EXT_CLK_SEL refers to the specific bit field within the bit map The clock then runs through a prescaler The prescaler is controlled by an 8 bit register Register values from 0 to 255 correspond to dividing the clock by 1 to 2...

Page 398: ...bit or enable the interrupt When the capture occurs read the capture data register result TimerRegs T24CAPDAT bit CAP_DAT Then enable capture on the falling edge When the capture occurs read the capture data register again and subtract result TimerRegs T24CAPDAT bit CAP_DAT result Note that overflow handling may be necessary as well This depends on the expected timing of the signal One simple solu...

Page 399: ...traightforward Refer to Section 11 21 for details 11 5 T24 Interrupts There are 4 or 5 T24 interrupts depending on the device Each one has a separate bit in the CIM Central Interrupt Module This means that each interrupt can have an independent interrupt vector with no need to read from the timer module to determine which interrupt has occurred On the UCD3138128A and UCD3138A64A the DTC interrupt ...

Page 400: ...ompare 0 block To enable this function use this C code TimerRegs T16PWM0CNTCTRL bit CMP_RESET_ENA 1 enable Comp 0 reset If this bit is set the counter will be reset when the counter reaches the value in the T16PWM0CMP0DAT bit CMP_DAT register The 16 bit counter can also be reset by setting the SW_RESET bit TimerRegs T16PWM0CNTCTRL bit SW_RESET 0 reset and stop counter A zero in SW_RESET is the def...

Page 401: ...n this case for one cycle the compare 1 event will not occur Normally for PWM compare 1 is used to turn off the PWM pulse So the result will be a PWM pulse that is on for the entire period If the SHADOW bit is set it enables buffer registers called shadow registers for the compare data registers The data written is stored in the shadow register until the next compare event and only then is it writ...

Page 402: ...ly 10 KHz Consult the UCD3138 device datasheet for ICLK speeds TimerRegs T16PWM0CMP0DAT bit CMP_DAT 1587 value to reset counter TimerRegs T16PWM0CMP1DAT bit CMP_DAT 793 50 50 duty cycle half of comp 0 TimerRegs T16PWM0CMPCTRL bit PWM_OUT_ACTION0 1 1 is for clear pin TimerRegs T16PWM0CMPCTRL bit PWM_OUT_ACTION1 2 2 is for clear pin TimerRegs T16PWM0CNTCTRL bit CMP_RESET_ENA 1 enable reset by comp 0...

Page 403: ...s 11 16 Watchdog Compare Blocks The two compare blocks are one for the counter half full and one for the counter overflow The half full counter interrupt is intended to give advance warning that something is wrong with program execution If the interrupt function is still working it can be used to start a recovery operation The counter overflow can also be used just as an interrupt or it can be con...

Page 404: ...hen poll the interrupt bits in the CIM to determine when the WD bits are set Then it is safe to read from the WD status register to clear the bits which will also clear the CIM bits Additionally please note the following the WAKE_EV_INT will be set at the halfway point and cleared on read of Watchdog Status Register all three bits in the WDST register may be set upon power up reset so they should ...

Page 405: ...ng attributes 32 bit wide Addresses placed on word boundaries Byte Half Word and word writes permitted All Registers can be read in any mode All Registers except for the Timer Powerdown Control Register are writeable in any mode The Timer Powerdown Control Register is writeable only in privilege mode 11 21 1 24 bit Counter Data Register T24CNTDAT Address FFF7FD00 Figure 11 4 24 bit Counter Data Re...

Page 406: ...0 0000 Defines the prescaler value used to select the 24 bit counter resolution The minimum divider ratio is 4 prescaler value less than 3 defaults to 3 Counter Resolution Prescaler Value 1 1 ICLK 7 3 Reserved R W 00000 2 EXT_CLK_SEL R W 0 External Clock Select 0 Selects ICLK as clock for 24 bit counter Default 1 Selects External Clock on FAULT 0 as clock for 24 bit counter 1 OV_INT_ENA R W 0 Coun...

Page 407: ... bit Capture Data Register 0 Address FFF7FD0C 24 bit Capture Data Register 1 only on A64 and 128 The a64 and 128 devices have T24CAPDAT0 and 1 Other devices have T24CAPDAT Figure 11 6 24 bit Capture Channel Data Register T24CAPDAT 23 0 CAP_DAT R 0 LEGEND R W Read Write R Read only n value after reset Table 11 3 24 bit Capture Channel Data Register T24CAPDAT Register Field Descriptions Bit Field Ty...

Page 408: ... after reset Table 11 4 24 bit Capture Channel Control Register T24CAPCTRL Register Field Descriptions Bit Field Type Reset Description 5 4 CAP_SEL R W 00 Capture Pin Select 00 TCAP pin Default 01 SCI_RX 0 pin 10 SCI_RX 1 pin 11 SYNC pin 3 2 EDGE R W 00 Input Capture Edge Select 00 No Capture Default 01 Rising Edge 10 Falling Edge 11 Both Edges 1 CAP_INT_ENA R W 0 Input Capture Interrupt Enable 0 ...

Page 409: ...nput data for pin TCAP_1 TDI TDO pin when connected to chip I O 0 Logic level low detected on TCAP pin 1 Logic level high detected on TCAP pin 4 TCAP_OUT R W 0 Output data for pin TCAP_1 pin when connected to chip I O 0 Logic level low driven on TCAP_1 pin in output mode Default 1 Logic level high driven on TCAP_1 pin in output mode 3 TCAP_1_DIR R W 0 Controls data direction for pin TCAP when conn...

Page 410: ...ata Register T24CMPDAT0 Address FFF7FD24 Figure 11 9 24 bit Output Compare Channel 0 Data Register T24CMPDAT0 23 0 CMP_DAT R W 0000 0000 0000 0000 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 11 6 24 bit Output Compare Channel 0 Data Register T24CMPDAT0 Register Field Descriptions Bit Field Type Reset Description 23 0 CMP_DAT R W 0000 0000 0000 0000 0000 0000 Contains the ...

Page 411: ...ta Register T24CMPDAT1 Address FFF7FD28 Figure 11 10 24 bit Output Compare Channel 1 Data Register T24CMPDAT1 23 0 CMP_DAT R W 0000 0000 0000 0000 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 11 7 24 bit Output Compare Channel 1 Data Register T24CMPDAT1 Register Field Descriptions Bit Field Type Reset Description 23 01 CMP_DAT R W 0000 0000 0000 0000 0000 0000 Contains the...

Page 412: ...er reset Table 11 8 24 bit Output Compare Channel 0 Control Register T24CMPCTRL0 Register Field Descriptions Bit Field Type Reset Description 1 CMP_INT_ENA R W 0 Output Compare Channel Interrupt 0 Disables Output Compare Channel Interrupt Default 1 Enables Output Compare Channel Interrupt 0 CMP_INT_FLAG R W 0 Indicates a valid output compare event Bit can be cleared by writing a 1 to the bit or by...

Page 413: ...er reset Table 11 9 24 bit Output Compare Channel 1 Control Register T24CMPCTRL1 Register Field Descriptions Bit Field Type Reset Description 1 CMP_INT_ENA R W 0 Output Compare Channel Interrupt 0 Disables Output Compare Channel Interrupt Default 1 Enables Output Compare Channel Interrupt 0 CMP_INT_FLAG R W 0 Indicates a valid output compare event Bit can be cleared by writing a 1 to the bit or by...

Page 414: ...nter Data Register Address FFF7FD58 16 bit PWM1 Counter Data Register Address FFF7FD6C 16 bit PWM2 Counter Data Register Address FFF7FD80 16 bit PWM3 Counter Data Register Figure 11 13 PWMx Counter Data Register T16PWMxCNTDAT 15 0 CNT_DAT R 0 LEGEND R W Read Write R Read only n value after reset Table 11 10 PWMx Counter Data Register T16PWMxCNTDAT Register Field Descriptions Bit Field Type Reset D...

Page 415: ...Resolution Prescaler 1 1 ICLK 7 Reserved R 0 6 5 SYNC_SEL R W 00 Configures master PWM counter 0 PWM0 Counter Default 1 PWM1 Counter 2 PWM2 Counter 3 PWM3 Counter 4 SYNC_EN R W 0 PWM counter starts when master PWM counter is enabled 0 PWM counter independent of other PWM counters Default 1 PWM counter controlled by Master PWM counter 3 SW_RESET R W 0 PWM counter reset by software This bit is clear...

Page 416: ... Register Address FFF7FD8C 16 bit PWM3 Compare Channel 1 Data Register Figure 11 15 PWMx 16 bit Compare Channel 0 1 Data Register T16PWMxCMPyDAT 15 0 CMP_DAT R W 0000 0000 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 11 12 PWMx 16 bit Compare Channel 0 1 Data Register T16PWMxCMPyDAT Register Field Descriptions Bit Field Type Reset Description 15 0 CMP_DAT R W 0000 0000 000...

Page 417: ... 0 Controls the update of the 16 bit output compare Registers 0 PWM output compare Registers immediately written Default 1 PWM output compare Registers updated through the buffers T16PWMxCMPyDAT after a match occurs in the corresponding Register T16PWMxCMPyDAT 11 PWM_IN R 0 Input value of PWM pin when configured in PWM mode 0 Logic level low detected on PWM pin 1 Logic level high detected on PWM p...

Page 418: ...s bit is cleared by writing 1 to this bit or by rewriting T16PWMxCMP1DAT If a clear and a compare event occurs at the same time the flag will remain high set has priority versus write clear 0 No compare event since last clear 1 Compare event since last clear 1 CMP0_INT_ENA R W 0 Compare 0 Interrupt Enable 0 Disables Compare 0 Interrupt Default 1 Enables Compare 0 Interrupt 0 CMP0_INT_FLAG R W 0 Fl...

Page 419: ...Description 3 WAKE_EV_RAW R 0 Watchdog Wake Event Raw Status 0 Watchdog Timer has not reached of terminal count 1 Watchdog Timer has reached of terminal count 2 WD_EV_RAW R 0 Watchdog Event Raw Status 0 Watchdog Timer has not reached terminal count 1 Watchdog Timer has reached terminal count 1 WAKE_EV_INT R 0 Watchdog Wake Event Interrupt Status cleared on read of Watchdog Status Register 0 Watchd...

Page 420: ...it 5 WDRST_ENA Bit 2 and WKEV_ENA Bit 1 are automatically set high when PROTECT is written low 1 Watchdog enable bits can be set by processor Default 5 CPU_RESET_EN R W 0 Enables Watchdog Reset Event to reset the CPU 0 Watchdog Reset does not reset CPU Default 1 Watchdog Reset does resets CPU 4 WDRST_INT_EN R W 0 Watchdog Reset Event Interrupt Enable 0 Disables generation of Watchdog Reset Interru...

Page 421: ... the standard non return to zero format The UART module can be used to communicate for example through an RS 232 port or over a K line Pins SCI_Rx UART receive pin SCI_Tx UART transmit pin Interrupts The UART has three interrupts transmit receive and error Each interrupt can be individually enabled Features Standard universal asynchronous receiver transmitter UART communication Supports full or ha...

Page 422: ...it therefore consists of 8 samples one for each clock period When the UART is using asynchronous mode the baud rates of all communicating devices must match as closely as possible Receive errors result from devices communicating at different baud rates With the receiver in the asynchronous timing mode the UART detects a valid start bit if the first four samples after a falling edge on the SCI_RX p...

Page 423: ... 0 6 91 2400 0 3 45 4800 0 1 150 9600 0 0 202 19200 0 0 101 38400 0 0 50 57600 0 0 33 115200 0 0 16 230400 0 0 7 460800 0 0 3 921600 0 0 1 12 3 UART Interrupts The UART receiver and transmitter can be controlled by interrupts The receive and transmit interrupts allow efficient operation of the UART by reading and writing character information to and from the UART as new data arrives and when old d...

Page 424: ...bit If the TX_INT_ENA bit UARTCTRL3 3 is set then a transmit interrupt is generated when the TXRDY flag goes high Writing data to the UARTTXBUF register clears the TXRDY bit When this data has been moved to the UARTTXSHF register the TXRDY bit is set again The interrupt request can be suspended by clearing the TX_INT_ENA bit however when the TX_INT_ENA bit is again set to 1 the TXRDY interrupt is ...

Page 425: ... by three separate enable bits RXERR_INT_ENA BRKDT_INT_ENA and WAKEUP_INT_ENA If RXERR_INT_ENA UARTCTRL3 0 is set an error interrupt is generated when the receiver detects either a parity framing or overrun error The break detect interrupt is enabled separately If BRKDT_INT_ENA UARTCTRL3 1 is set an error interrupt is generated if the receiver detects a break condition A break condition occurs whe...

Page 426: ...R W 0 Configures stop bits for each frame 0 One STOP bit included in each frame Default 1 Two STOP bits included in each frame 6 PARITY R W 0 Sets odd or even parity 0 Even parity Default 1 Odd parity 5 PARITY_ENA R W 0 Enables parity transmission 0 No parity bit included in each frame Default 1 One parity bit included in each frame 4 SYNC_MODE R W 0 Selects between Synchronous mode and Asynchrono...

Page 427: ...D R W Read Write R Read only n value after reset Table 12 3 UART Receive Status Register UARTRXST Register Field Descriptions Bit Field Type Reset Description 4 RX_IDLE R 0 RX Idle status bit 0 Not in Rx Idle State 1 Rx Idle detected 3 SLEEP R W 0 Sleep Mode Configuration 0 Sleep Mode disabled Default 1 Sleep Mode enabled 2 RX_RDY R 0 UART Receiver ready status bit 0 UART Receiver not ready 1 UART...

Page 428: ...ansmit Status Register UARTTXST Register Field Descriptions Bit Field Type Reset Description 7 CONTINUE R W 0 Configure operation in suspend mode 0 Stop transmitting on suspend Default 1 Continue transmitting after initiation of suspend 6 LOOPBACK R W 0 Loopback Mode Configuration 0 Normal mode Default 1 Loopback Mode 5 4 Reserved R 00 3 TX_EMPTY R 0 Transmit buffer status 0 Transmit buffer is not...

Page 429: ...s Software Reset 6 POWERDOWN R W 0 Power down Transmitter Receiver Control 0 Disables Power down mode Default 1 Enables Power down mode 5 CLOCK R W 0 UART Clock Select 0 Selects external clock Default 1 Selects internal clock 4 RX_INT_ENA R W 0 Enables the interrupts from UART Receiver 0 Disables interrupts from UART Receiver Default 1 Enables interrupts from UART Receiver 3 TX_INT_ENA R W 0 Enabl...

Page 430: ...T Receiver ready to accept new frame 1 UART Receiver currently processing message 6 Reserved R 0 5 FRAME_ERR R C 0 UART Receiver Framing Error 0 No framing error found within incoming data message 1 Indicates the incoming data message had a framing error 4 OVERRUN_ERR R C 0 UART Receiver Buffer Overflow 0 No overflow condition found in receive buffer 1 Indicates the receive buffer has overflowed 3...

Page 431: ...814 UART 0 Baud Divisor High Byte Register Address FFF7D914 UART 1 Baud Divisor High Byte Register Figure 12 8 UART Baud Divisor High Byte Register UARTHBAUD 7 0 BAUD_DIV_H R W 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 12 7 UART Baud Divisor High Byte Register UARTHBAUD Register Field Descriptions Bit Field Type Reset Description 7 0 BAUD_DIV_H R W 0000 0000 Sets the hi...

Page 432: ...UART 0 Baud Divisor Middle Byte Register Address FFF7D918 UART 1 Baud Divisor Middle Byte Register Figure 12 9 UART Baud Divisor Middle Byte Register UARTMBAUD 7 0 BAUD_DIV_M R W 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 12 8 UART Baud Divisor Middle Byte Register UARTMBAUD Register Field Descriptions Bit Field Type Reset Description 7 0 BAUD_DIV_M R W 0000 0000 Sets th...

Page 433: ...7D81C UART 0 Baud Divisor Low Byte Register Address FFF7D91C UART 1 Baud Divisor Low Byte Register Figure 12 10 UART Baud Divisor Low Byte Register UARTLBAUD 7 0 BAUD_DIV_L R W 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 12 9 UART Baud Divisor Low Byte Register UARTLBAUD Register Field Descriptions Bit Field Type Reset Description 7 0 BAUD_DIV_L R W 0000 0000 Sets the low...

Page 434: ...ceive Buffer UARTRXBUF Address FFF7D824 UART 0 Receive Buffer Address FFF7D924 UART 1 Receive Buffer Figure 12 11 UART Receive Buffer UARTRXBUF 7 0 RXDAT R 0 LEGEND R W Read Write R Read only n value after reset Table 12 10 UART Receive Buffer UARTRXBUF Register Field Descriptions Bit Field Type Reset Description 7 0 RXDAT R 0 Contains the last data byte received from the UART Receiver ...

Page 435: ...ARTTXBUF Address FFF7D828 UART 0 Transmit Buffer Address FFF7D928 UART 1 Transmit Buffer Figure 12 12 UART Transmit Buffer UARTTXBUF 7 0 TXDAT R W 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 12 11 UART Transmit Buffer UARTTXBUF Register Field Descriptions Bit Field Type Reset Description 7 0 TXDAT R W 0000 0000 Contains the data byte to be transmitted by the UART Transmit...

Page 436: ...7D934 UART 1 I O TX Control Register Figure 12 13 UART I O Control Register UARTIOCTRLSCLK UARTIOCTRLRX UARTIOCTRLTX 3 2 1 0 DATA_IN DATA_OUT IO_FUNC IO_DIR R 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 12 12 UART I O Control Register UARTIOCTRLSCLK UARTIOCTRLRX UARTIOCTRLTX Register Field Descriptions Bit Field Type Reset Description 3 DATA_IN R 0 Data received...

Page 437: ...d download programs into the device They also offer security for production programs CAUTION Programming the checksum in the Flash without proper precautions can render the UCD3138 in state where it is not re programmable any further To avoid program flash lockout see Section 3 1 4 Topic Page 13 1 Boot ROM Function 438 13 2 Memory Read Functionality 441 13 3 Read Version 442 13 4 Memory Write Func...

Page 438: ...e Program Flash The 32K checksum verification takes about 10 milliseconds to complete The checksum is a simple additive checksum Each byte in memory is treated as a positive 8 bit number and is added to the checksum A 4 byte checksum is used so no truncation occurs Even if the entire memory is full of 0xff the checksum value will only be 0x7F7C04 The checksum calculation includes all the bytes in ...

Page 439: ...All of these tasks can actually be accomplished with the Program Flash checksum as well so long as the upgrade is not interrupted If the upgrade is interrupted before it is complete the Program Flash checksum will not be correct and the Boot ROM will not pass control to the Program Flash With the Boot ROM only the first 2K of the program flash must be correct The customer program in the Boot Flash...

Page 440: ...ding Program Flash Lockup If either checksum is programmed correctly the Boot ROM will turn control directly over to the Program Flash This is necessary for product startup in production units It also provides security for the program because the Boot ROM cannot be used to read from the Program Flash Even in production programs a backdoor is often added to the program to enable clearing the checks...

Page 441: ...ed by the slave These commands make it possible to read from any valid memory location They can be used to read from peripheral registers as well as from memories 13 2 1 Configure Read Address Since the read commands only provide a command code it is first necessary to provide an address to read from The read address is set up through a PMBus Write Block message with a command byte of 0xFD Startin...

Page 442: ...at multiple memory reads do not require multiple Configure Read Address Commands A Read Next Block message must be preceded by either a Read Block Message or a Read Next Block Message The read address is initially configured prior to the Read Block message that starts the data transfer The master initiates the Read Next Block message by sending a device address and a command byte of 0xF8 The Boot ...

Page 443: ...the word at the write address specified by the incoming message Start Device Address R W 0x16 Command Byte 0xF5 Block Size 0x08 Write Address 31 24 Write Address 24 16 Write Address 15 8 Write Address 7 0 Data 31 24 Data 23 16 Data 15 8 Data 7 0 PEC Stop The Write 4 Bytes message is normally very quick and no PMBus delay is required However the Write 4 Bytes message can be used for writing to data...

Page 444: ...red However the Write Next 16 Bytes message can be used for writing to data and program flash simply by writing to the appropriate address In this case 200 µsec should be allowed before starting the next message 13 5 Flash Functions In addition to the ability to read and write internal memory map locations the UCD3138 Boot ROM supports flash functions These functions allow the user to perform a ma...

Page 445: ...page erase of either the Program or Data Flash through a PMBus message The PMBus Master initiates a PMBus write block message to the UCD3138 The master initiates the message by sending the device address a command byte of 0xF1 a block length of 0x4 four data bytes and a PEC byte The first data byte selects which flash memory in which the page erase will be performed The next byte selects the page ...

Page 446: ...ocks to address 0 Table 13 3 Boot ROM Execute Flash Command Byte Valid Values 1 Command Byte 0xF0 Command Byte 0xF7 UCD3138 UCD3138A pflash 0x0000 to 0x7FFF not valid UCD3130A64 UCD3138064A pflash block 1 0x0000 to 0x7FFF pflash block 1 0x8000 to 0xFFFF pflash block 2 0x8000 to 0xFFFF pflash block 2 0x0000 to 0x7FFF UCD3138A64 UCD3138A64A pflash block 0 0x0000 to 0x7FFF not valid pflash block 1 0x...

Page 447: ...dress a command byte of 0xEE The UCD3138 returns the four checksum bytes and a PEC byte Upon detection of the command byte 0xEE the Boot ROM reads the calculated checksum and returns to the PMBus master Start Device Address R W 0x16 Command Byte 0xEE Block Size 0x04 Checksum 31 24 Checksum 23 16 Checksum 15 8 Checksum 7 0 PEC Stop 13 7 Trim Flash Checksum Verification The Boot ROM also initializes...

Page 448: ...cksum locations in Table 13 4 assume that program flash block 1 is mapped to address 0x0000 and program flash block 2 is mapped to 0x8000 Figure 13 3 UCD3138064 Boot ROM Execution After Power on Reset Figure 13 3 is a flowchart showing the order in which the ROM verifies the integrity of the program flash contents using the different checksums The branch instruction check at the very beginning pre...

Page 449: ... checksum rather than the sum of 8 bit bytes This makes the checksum calculation approximately 4 times faster It means that the Boot ROM program can verify the checksum for 64kB in around 5ms while the UCD3138 Boot ROM program takes 10ms to verify 32kB of program flash Here is the code for calculating the checksum void calculate_checksum register Uint32 start_address register Uint32 end_address us...

Page 450: ...his can still be done however using a boot flash program Or the program in block 0 can be a fixed program which checks the program in block 1 and jumps to it if appropriate 13 8 3 UCD3138128 and UCD3138128A The UCD3138128 uses checksums to verify the integrity of the first 2kB 32kB and 64kB of program flash just like the UCD3138A64 It also has checksums to verify the second 64kB and for the full 1...

Page 451: ... Otherwise a block filled with zeroes would pass the checksum test The UCD3138 has a PMBus command called execute flash with a command code of 0xF0 This causes the program to execute On the UCD3138128 the same command code cause program flash block 0 to be mapped to address 0x00000 program flash block 1 to be mapped to address 0x08000 program flash block 2 to be mapped to address 0x10000 program f...

Page 452: ...ciples where two instruction sets are available the 32 bit ARM instruction set and the 16 bit Thumb instruction set The Thumb instruction allows for higher code density equivalent to a 16 bit microprocessor with the performance of the 32 bit microprocessor The three staged pipelined ARM processor is architected with fetch decode and execute stages Major blocks in the ARM processor include a 32 bit...

Page 453: ...e ARM processor has a simple privilege model all modes are privileged apart from User mode Privilege is the ability to perform certain tasks that cannot be done from User mode For example changing the operating mode is a privileged operation The ARM processor has a total of 37 registers 31 general purpose registers including the Program Counter R15 and 6 status registers These registers are shown ...

Page 454: ...bit 7 disables the normal Interrupt IRQ These bits can only be modified in a privileged mode Bit 5 the T bit determines whether the processor runs in ARM state or in Thumb state Thumb state uses a different more compact instruction set when compared to ARM Never set this bit Doing so will make the processor enter an unpredictable state This bit can only be modified in a privileged mode Bits 0 4 se...

Page 455: ...te from Table 14 5 that there is just enough room at each vector address for one instruction 4 bytes This is usually initialized to be a branch instruction or something like ldr pc pc 24 Table 14 5 ARM Processor Exceptions Exception Type Processor Mode Vector Address Reset Supervisor 0x0000000 Undefined Instructions Undefined 0x0000004 Software Interrupt swi Supervisor 0x0000008 Prefetch Abort ins...

Page 456: ...oftware interrupt is initiated by the sequential execution of the software and by calling a specific function The call to a software interrupt function looks identical to a call to any other standard function Declaration of a new function and its mapping to software interrupt is done through aliasing pragma pragma SWI_ALIAS erase_data_flash_segment 0 void erase_data_flash_segment Uint8 segment The...

Page 457: ...mpressed to full 32 bit ARM instructions in real time without performance loss Thumb has all the advantages of a 32 bit core 32 bit address space 32 bit registers 32 bit shifter and Arithmetic Logic Unit ALU 32 bit memory transfer Therefore Thumb offers a long branch range powerful arithmetic operations and a large address space The availability of both 16 bit Thumb and 32 bit ARM instruction sets...

Page 458: ...upport can directly call the following functions Functions complied in the same state Functions in a different state that support dual state interworking Functions with this support level can indirectly call only functions that do not require a state change and do not support dual state interworking Because functions with this support level do not provide dual state interworking they cannot be cal...

Page 459: ...S state entry point to the function with bit 0 of the address set Likewise addresses of functions taken in 32 BIS state use the address of the 32 BIS state entry point with bit 0 of the address cleared Then all indirect calls are performed by loading the address of the called function into a register and executing the branch and exchange BX instruction This automatically changes the state and ensu...

Page 460: ...le 1 Code Compiled for 16 BIS State Sum C Program int total 0 sum int val1 int val2 int val max val1 val2 total val 16 bit assembly program function venner _sum _sum state32 STMFD sp lr ADD lr pc 1 BX lr state16 BL sum BX pc NOP state16 sect text global sum function def sum sum PUSH LR BL max LDR A2 CON1 LDR A3 A2 0 ADD A1 A1 A3 STR A1 A2 0 POP PC constant table sect text align4 ...

Page 461: ...ill have the same structure but the functions all have underscore as their first character whether they are in ARM or Thumb mode The assembler knows the mode by the setting at assembly time This information is stored in the object file and the linker actually inserts the code for mode switching It is no longer compiled around each function as in 3 3 14 5 5 UCD3138 Reference Code The UCD3138 refere...

Page 462: ...d to build parts of the code in ARM or Thumb mode This is done through utilization of code_state 16 32 or mt compiler build options code_state 16 32 Designates code state as 16 bit thumb or default 32 bit arm mt Designates code state as 16 bit thumb mode Therefore code_state 16 and mt have identical effect Figure 14 1 shows the build options for the entire project Figure 14 1 It can be seen that t...

Page 463: ... in ARM mode in order to minimize the ISR execution latencies Interrupts all start out in ARM mode the interrupt hardware changes the state to ARM mode It is preferred to stay in ARM mode even when executing the functions called by any of the interrupt service routines These functions are located in the file interrupt c Figure 14 3 shows the file specific build options for the file interrupts c wh...

Page 464: ...ch to ARM mode when executing this specific part of the code And the ARM mode instruction set will be used to perform this section of the code For additional information please refer to the following reference material ARM Optimizing C C Compiler v5 2 User s Guide SPNU151 ARM Assembly Language Tools v5 2 CCS 6 SPNU118 ARM7TDMI S Technical Reference Manual http infocenter arm com help topic com arm...

Page 465: ...rase for erasing the entire program FLASH array The FLASH endurance is specified at 1000 erase write cycles and the data retention is good for 100 years The 2KB Data FLASH array is organized as a 512x32 memory The Data FLASH is intended for firmware data value storage and data logging Thus the Data FLASH is specified as a high endurance memory of 20K cycles with embedded ECC Error correction code ...

Page 466: ...d non A versions With all the rest of the devices the A and non A memory maps are the same Mode 1 and Mode 2 are provided so that multiple versions can be supported by the Boot ROM The put different flash blocks or pairs of flash blocks at location 0 The Data Flash and RAM are always in the same locations regardless of ROM or FLASH mode Table 15 3 RAM and Data Flash Memory Map ROM and Flash Operat...

Page 467: ...s Analog Control Peripheral Select 3 0xFFF7_F600 0xFFF7_F6FF 256 PMBus Interface Peripheral Select 2 0xFFF7_FA00 0xFFF7_FAFF 256 GIO Peripheral Select 1 0xFFF7_FD00 0xFFF7_FDFF 256 Timer Peripheral Select 0 0xFFFF_FD00 0xFFFF_FDFF 256 MMC SAR Select 2 0xFFFF_FE00 0xFFFF_FEFF 256 DEC SAR Select 1 0xFFFF_FF20 0xFFFF_FF37 23 CIM SAR Select 0 0xFFFF_FF40 0xFFFF_FF50 16 PSA SAR Select 0 0xFFFF_FFD0 0xF...

Page 468: ...l Register SMCTRL Register Field Descriptions Bit Field Type Reset Description 13 12 LEAD R W 00 Address setup time cycles write operations 00 No setup time required Default 01 Write strobe is delayed one cycle 10 Write strobe is delayed two cycles 11 Write strobe is delayed three cycles 11 9 TRAIL R W 000 Number of Trailing wait states Determine the trailing wait states after read and write opera...

Page 469: ...16 Submit Documentation Feedback Copyright 2016 Texas Instruments Incorporated Memory Table 15 5 Static Memory Control Register SMCTRL Register Field Descriptions continued Bit Field Type Reset Description 1 0 WIDTH R W 00 Data Width for Memories 00 8 bits Default 01 16 bits 10 32 bits 11 Reserved ...

Page 470: ...TRL Register Field Descriptions Bit Field Type Reset Description 1 TRAIL_OVR R W 0 Write trailing wait state override 0 At least one trailing wait state Default 1 TRAIL sets trailing wait states 0 WBUF_ENA R W 0 Write buffer enable When this bit is 1 the memory controller latches the data and control signals in the first cycle for write operations to the memories and peripherals on the expansion b...

Page 471: ...n value after reset Table 15 7 Peripheral Control Register PCTRL Register Field Descriptions Bit Field Type Reset Description 0 PUBF_ENA R W 0 Write buffer enable When this bit is set to 1 the memory controller latches the data and control signals in the first cycle for write operations to the memories and peripherals on the expansion bus and lets the CPU perform other operations However the CPU s...

Page 472: ...34 Figure 15 4 Peripheral Location Register PLOC 15 0 LOC R W 0000 0000 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 15 8 Peripheral Location Register PLOC Register Field Descriptions Bit Field Type Reset Description 15 0 LOC R W 0000 0000 0000 0000 These 16 bits represent the peripheral location bits which correspond to each of the 16 peripheral selects 0 Peripheral is in...

Page 473: ...signals by decoding the address and control signals from the ARM processor In addition the DEC provides the control signals for the Program and Data Flash The assigned memory selects for UCD3138 are as follows Memory Select 0 Boot ROM 1Kx32 Memory Select 1 Program Flash 8Kx32 Memory Select 2 Data Flash 512x32 Memory Select 3 Data RAM 1Kx32 Memory Select 4 Loop Mux 1Kx32 Memory Select 5 Fault Mux 1...

Page 474: ...Address High Register 0 MFBAHR0 15 0 ADDRESS 31 16 R W 0000 0000 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 15 10 Memory Fine Base Address High Register 0 MFBAHR0 Register Field Descriptions Bit Field Type Reset Description 15 0 ADDRESS 31 16 R W 0000 0000 0000 0000 16 Most Significant Bits of the Base Address The Base Address sets the 22 most significant bits of the mem...

Page 475: ...elect 0 Memory Map configuration not updated Default 1 Enables the fine and coarse memory selects and activates the memory map 7 4 BLOCK_SIZE R W 0000 Configures the size of the memory 0000 Memory select is disabled Default 0001 1KB 0010 2KB 0011 4KB 0100 8KB 0101 16KB 0110 32KB 0111 64KB 1000 128KB 1001 256KB 1010 512KB 1011 1MB 1100 2MB 1101 4MB 1110 8MB 1111 16MB 1 RONLY R W 0 Read only protect...

Page 476: ...y Fine Base Address High Register 17 not on 3138 Address FFFFFEA8 Memory Fine Base Address High Register 18 only on 128 Address FFFFFEB0 Memory Fine Base Address High Register 19 only on 128 Figure 15 8 Memory Fine Base Address High Register 1 3 17 19 MFBAHRx 15 0 ADDRESS 31 16 R W 0000 0000 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 15 12 Memory Fine Base Address High R...

Page 477: ... R W 000000 6 Least Significant Bits of the Base Address The Base Address sets the 22 most significant bits of the memory address 9 AW R W 0 Auto wait on write When this bit is set any write operation on this memory select takes two system cycles 0 Write operation is not supplemented with an additional cycle Default 1 Write operation takes an additional cycle 7 4 BLOCK_SIZE R W 0000 Configures the...

Page 478: ...ed Memory 15 2 5 Memory Fine Base Address High Load Differences for Enhanced 3138 Devices These tables show the values loaded into the registers in the UCD3138 To make room for additional Program Flash in the UCD3138064 and other devices with more program flash the registers have an additional bit set that moves the peripherals to start at 0x120000 instead of at 0x20000 ...

Page 479: ...se Address High Register 4 Figure 15 10 Memory Fine Base Address High Register 4 MFBAHR4 15 0 ADDRESS 31 16 R W 0000 0000 0000 0010 LEGEND R W Read Write R Read only n value after reset Table 15 14 Memory Fine Base Address High Register 4 MFBAHR4 Register Field Descriptions Bit Field Type Reset Description 15 0 ADDRESS 31 16 R W 0000 0000 0000 0010 16 Most Significant Bits of the Base Address The ...

Page 480: ... 8 2 1 0 ADDRESS 15 10 AW Reserved RONLY PRIV R W 000000 R W 0 R W 0 0000 00 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 15 15 Memory Fine Base Address Low Register 4 17 MFBALRx Register Field Descriptions Bit Field Type Reset Description 15 10 ADDRESS 15 10 R W 000000 6 Least Significant Bits of the Base Address The Base Address sets the 22 most significant bits of the...

Page 481: ...se Address High Register 5 Figure 15 12 Memory Fine Base Address High Register 5 MFBAHR5 15 0 ADDRESS 31 16 R W 0000 0000 0000 0011 LEGEND R W Read Write R Read only n value after reset Table 15 16 Memory Fine Base Address High Register 5 MFBAHR5 Register Field Descriptions Bit Field Type Reset Description 15 0 ADDRESS 31 16 R W 0000 0000 0000 0011 16 Most Significant Bits of the Base Address The ...

Page 482: ...se Address High Register 6 Figure 15 13 Memory Fine Base Address High Register 6 MFBAHR6 15 0 ADDRESS 31 16 R W 0000 0000 0000 0100 LEGEND R W Read Write R Read only n value after reset Table 15 17 Memory Fine Base Address High Register 6 MFBAHR6 Register Field Descriptions Bit Field Type Reset Description 15 0 ADDRESS 31 16 R W 0000 0000 0000 0100 16 Most Significant Bits of the Base Address The ...

Page 483: ...ase Address High Register 7 Figure 15 14 Memory Fine Base Address High Register 7 MFBAHR7 15 0 ADDRESS 31 16 R W 0000 0000 0000 0101 LEGEND R W Read Write R Read only n value after reset Table 15 18 Memory Fine Base Address High Register 7 MFBAHR7 Register Field Descriptions Bit Field Type Reset Description 15 0 ADDRESS 31 16 R W 0000 0000 0000 0101 16 Most Significant Bits of the Base Address The...

Page 484: ...ase Address High Register 8 Figure 15 15 Memory Fine Base Address High Register 8 MFBAHR8 15 0 ADDRESS 31 16 R W 0000 0000 0000 0110 LEGEND R W Read Write R Read only n value after reset Table 15 19 Memory Fine Base Address High Register 8 MFBAHR8 Register Field Descriptions Bit Field Type Reset Description 15 0 ADDRESS 31 16 R W 0000 0000 0000 0110 16 Most Significant Bits of the Base Address The...

Page 485: ...ase Address High Register 9 Figure 15 16 Memory Fine Base Address High Register 9 MFBAHR9 15 0 ADDRESS 31 16 R W 0000 0000 0000 0111 LEGEND R W Read Write R Read only n value after reset Table 15 20 Memory Fine Base Address High Register 9 MFBAHR9 Register Field Descriptions Bit Field Type Reset Description 15 0 ADDRESS 31 16 R W 0000 0000 0000 0111 16 Most Significant Bits of the Base Address The...

Page 486: ...e Address High Register 10 Figure 15 17 Memory Fine Base Address High Register 10 MFBAHR10 15 0 ADDRESS 31 16 R W 0000 0000 0000 1000 LEGEND R W Read Write R Read only n value after reset Table 15 21 Memory Fine Base Address High Register 10 MFBAHR10 Register Field Descriptions Bit Field Type Reset Description 15 0 ADDRESS 31 16 R W 0000 0000 0000 1000 16 Most Significant Bits of the Base Address ...

Page 487: ...e Address High Register 11 Figure 15 18 Memory Fine Base Address High Register 11 MFBAHR11 15 0 ADDRESS 31 16 R W 0000 0000 0000 1001 LEGEND R W Read Write R Read only n value after reset Table 15 22 Memory Fine Base Address High Register 11 MFBAHR11 Register Field Descriptions Bit Field Type Reset Description 15 0 ADDRESS 31 16 R W 0000 0000 0000 1001 16 Most Significant Bits of the Base Address ...

Page 488: ...e Address High Register 12 Figure 15 19 Memory Fine Base Address High Register 12 MFBAHR12 15 0 ADDRESS 31 16 R W 0000 0000 0000 1010 LEGEND R W Read Write R Read only n value after reset Table 15 23 Memory Fine Base Address High Register 12 MFBAHR12 Register Field Descriptions Bit Field Type Reset Description 15 0 ADDRESS 31 16 R W 0000 0000 0000 1010 16 Most Significant Bits of the Base Address ...

Page 489: ...e Address High Register 13 Figure 15 20 Memory Fine Base Address High Register 13 MFBAHR13 15 0 ADDRESS 31 16 R W 0000 0000 0000 1011 LEGEND R W Read Write R Read only n value after reset Table 15 24 Memory Fine Base Address High Register 13 MFBAHR13 Register Field Descriptions Bit Field Type Reset Description 15 0 ADDRESS 31 16 R W 0000 0000 0000 1011 16 Most Significant Bits of the Base Address ...

Page 490: ...e Address High Register 14 Figure 15 21 Memory Fine Base Address High Register 14 MFBAHR14 15 0 ADDRESS 31 16 R W 0000 0000 0000 1100 LEGEND R W Read Write R Read only n value after reset Table 15 25 Memory Fine Base Address High Register 14 MFBAHR14 Register Field Descriptions Bit Field Type Reset Description 15 0 ADDRESS 31 16 R W 0000 0000 0000 1100 16 Most Significant Bits of the Base Address ...

Page 491: ...e Address High Register 15 Figure 15 22 Memory Fine Base Address High Register 15 MFBAHR15 15 0 ADDRESS 31 16 R W 0000 0000 0000 1101 LEGEND R W Read Write R Read only n value after reset Table 15 26 Memory Fine Base Address High Register 15 MFBAHR15 Register Field Descriptions Bit Field Type Reset Description 15 0 ADDRESS 31 16 R W 0000 0000 0000 1101 16 Most Significant Bits of the Base Address ...

Page 492: ...e Address High Register 16 Figure 15 23 Memory Fine Base Address High Register 16 MFBAHR16 15 0 ADDRESS 31 16 R W 0000 0000 0000 1110 LEGEND R W Read Write R Read only n value after reset Table 15 27 Memory Fine Base Address High Register 16 MFBAHR16 Register Field Descriptions Bit Field Type Reset Description 15 0 ADDRESS 31 16 R W 0000 0000 0000 1110 16 Most Significant Bits of the Base Address ...

Page 493: ...TRL Register Field Descriptions Bit Field Type Reset Description 11 BUSY R 0 Program Flash Busy Indicator 0 Program Flash available for read write erase access 1 Program Flash unavailable for read write erase access 10 Reserved R 0 9 PAGE_ERASE R W 0 Program Flash Page Erase Enable 0 No Page Erase initiated on Program Flash Default 1 Page Erase on Program Flash enabled Page erased is based on PAGE...

Page 494: ...ster Field Descriptions Bit Field Type Reset Description 11 BUSY R 0 Data Flash Busy Indicator 0 Data Flash available for read write erase access 1 Data Flash unavailable for read write erase access 10 Reserved R 0 9 PAGE_ERASE R W 0 Data Flash Page Erase Enable 0 No Page Erase initiated on Data Flash Default 1 Page Erase Cycle on Data Flash enabled Page erased is based on PAGE_SEL Bits 4 0 This b...

Page 495: ...ptions Bit Field Type Reset Description 31 0 INTERLOCK_KEY R W 0000 0000 0000 0000 0000 0000 0000 0000 Flash Interlock Key Register must be set to 0x42DC157E prior to every Data Flash write mass erase page erase or 0x42DC157E prior to every Program Flash 0 write mass erase page erase or 0x6C97D0C5 prior to every Program Flash 1 write mass erase page erase or 0x184219B3 prior to every Program Flash...

Page 496: ... write and erase of flash memory Provides control and monitoring of the interrupt signals from the peripherals Controls clocks software interrupts system exceptions The blocks inside the system module are the address decoder DecRegs memory control MMCRegs system management SysRegs and central interrupt CimRegs Topic Page 16 1 Address Decoder DEC 497 16 2 Memory Management Controller MMC 502 16 3 S...

Page 497: ...ilege mode for user mode protection The DEC Address Manager controls memory mapping and flash programming All memory mapping activity is normally done by the boot ROM This is described in this document This information is only useful if there is some need to return to ROM mode without going through a reset first There may be a need for customer programs to erase and program both Program and Data F...

Page 498: ...AM Program FLASH ROM ROM ROM always executes at 0xA000 except for Vectors Address Decoder DEC www ti com 498 SNIU028A February 2016 Revised April 2016 Submit Documentation Feedback Copyright 2016 Texas Instruments Incorporated Control System Module There are additional memory map registers for fast peripherals but these are never moved In addition several peripheral register sets including the Sys...

Page 499: ...nslates to 0x8800 A 0x24 translates to a 0x9000 There are other bits as well for example an RONLY bit signifying that the memory is read only There is also a MS for Memory Select bit in only MFBALR0 which enables the entire DEC module DEC stands for Memory Address DECode 16 1 4 RONLY Bit The DEC register has an RONLY bit as well If set this means read only An attempt to write to a memory space wit...

Page 500: ...zed in this pattern the ROM program performs a simple additive checksum on the Program Flash If the checksum matches the ROM program then reconfigures the memory map and jumps to location zero in the flash There is also a PMBus command that can command the ROM program to do the same thing This reconfiguration involves two steps 1 Remap the ROM to 0xA000 only 2 Remap the Program Flash to location 0...

Page 501: ...so it is possible to operate on data flash while executing from program flash It is not possible to read from data flash while writing or erasing data flash however So all values that will be needed during erase write process should be stored in RAM or program Flash The UCD3138 has 2048 bytes of Data flash organized in 64 blocks of 32 bytes each Erasing can be done a block at a time To erase a blo...

Page 502: ...ng the read and write accesses to each peripheral The unit generates eight peripheral select lines with 1KB of address space decoding The interface can be configured with an interface clock from divide by 2 thru 16 For divide by 2 each peripheral requires two clock accesses 16 3 System Management SYS The SYS unit contains the software access protection by configuring user privilege levels to memor...

Page 503: ...ed 12 FE2_INT Front End 2 Prebias complete Ramp Delay Complete Ramp Complete Load Step Detected Over Voltage Detected EADC saturated 13 PWM3_INT 16 bit Timer PWM 3 16 bit Timer PWM3 counter overflow or Compare interrupt 14 PWM2_INT 16 bit Timer PWM 2 16 bit Timer PWM2 counter Overflow or Compare interrupt 15 PWM1_INT 16 bit Timer PWM 1 16 bit Timer PWM1 counter overflow or Compare interrupt 16 PWM...

Page 504: ...R bit 7 When an FIQ interrupt is recognized the CPU disables both IRQ and FIQ interrupts by setting CPSR bits 6 and 7 After the interrupt is recognized by the CPU the program counter jumps to the appropriate interrupt vector 0x0018 for IRQ and 0x001C for FIQ 16 4 2 Interrupt Generation at Peripheral Interrupts begin when an event occurs within a peripheral module Some examples of interrupt capable...

Page 505: ... a channel by channel basis in the REQMASK register unused channels may be masked to prevent spurious interrupts Each interrupt channel can be designated to send either an FIQ or IRQ request to the CPU in the FIQPR register Interrupt Mask Register REQMASK and FIQ IRQ Program Control Register FIRQPR are writeable in privilege mode only A write in user mode to these Registers causes a peripheral ill...

Page 506: ... code example of calling these functions is shown below write_firqpr 0x0C000000 make them all irqs except dpwm4 and dpwm3 write_reqmask 0x0C010000 enable only pwm1cmp dpwm3 and dpwm4 16 4 5 CIM Prioritization The CIM prioritizes the received interrupts based upon a hardware and software prioritization scheme The software prioritization scheme is user configurable The CIM can send two interrupt req...

Page 507: ...emporary variable fiq_number The program should follow this format and should not read the CimRegs FIQIVEC repeatedly in the else if statements This is mostly because CimRegs FIQIVEC is a clear on read register therefore only the first read attempt per ISR of this register can be used to read intact and relevant values of all relevant bits The same is true about FaultMuxRegs FAULTMUXINTSTAT this i...

Page 508: ...ss FFFFFFD0 The clock control Register configures the MCLK divider for low power modes and the clock multiplexer which drives the Sync pin when configured to output the CLKOUT signal CLKCNTRL is accessible in user and privilege mode and supports byte half word and word accesses Any access to this Register takes two SYSCLK cycles Figure 16 4 Clock Control Register CLKCNTL 9 8 7 6 5 4 3 2 0 M_DIV_RA...

Page 509: ...exas Instruments Incorporated Control System Module Table 16 4 Clock Control Register CLKCNTL Register Field Descriptions continued Bit Field Type Reset Description 3 CLKDOUT R W 0 This pin represents the output value of CLKOUT 0 CLKOUT driven to logic low in output mode Default 1 CLKOUT driven to logic high in output mode 2 0 Reserved R 000 ...

Page 510: ...R W Read Write R Read only n value after reset Table 16 5 System Exception Control Register SYSECR Register Field Descriptions Bit Field Type Reset Description 15 14 RESET R W 01 Software Reset Enable These bits always read as 01 01 No reset 1X Global system reset X don t care X0 Global system reset X don t care 13 3 Reserved R 0 2 PACCOVR R W 0 Peripheral Access Violation Override 0 Peripheral ac...

Page 511: ... active Whenever a device is powered this bit is set User and privilege modes read 0 Power up reset has not occurred since the last clear 1 Power up reset has occurred since the last clear User and privilege modes write 0 Clears the corresponding bit to 0 1 No effect 14 CLKRST R W 0 This bit represents the clock fail flag This bit indicates a clock fault condition has occurred After power on reset...

Page 512: ...ge modes write 0 Clears the corresponding bit to 0 1 No effect 9 PILLACC R W 0 This bit represents the peripheral illegal access flag This bit is set when a peripheral access violation is detected in user mode User and privilege modes read 0 Illegal peripheral access has not occurred since the last clear 1 Illegal peripheral access has occurred since the last clear User and privilege modes write 0...

Page 513: ...s from either the MPU or system User and privilege modes read 0 No illegal address 1 Abort caused by an illegal address User and privilege modes write 0 Clears bit to 0 1 No effect 14 MEMABT R W 0 This bit represents the memory access abort This bit indicates an illegal memory access was detected in user mode An abort was generated due to the illegal memory access from either the MPU or system Use...

Page 514: ...he system detects an illegal address User and privilege modes read 0 No system illegal address 1 Abort or reset caused by a system illegal address User and privilege modes write 0 Clears bit to 0 1 No effect 6 SYSACC R W 0 This bit represents the system illegal access flag This bit is set when the system detects an illegal access User and privilege modes read 0 No system illegal access 1 Abort or ...

Page 515: ...e Identification Register contains device specification information that is hard coded during device manufacturing This register is read only Figure 16 9 Device Identification Register DEV 15 0 DEV R 0011 0100 0111 1111 LEGEND R W Read Write R Read only n value after reset Table 16 9 Device Identification Register DEV Register Field Descriptions Bit Field Type Reset Description 15 0 DEV R 0011 010...

Page 516: ... interrupt is triggered The flag allows the user to poll for a software interrupt Figure 16 10 System Software Interrupt Flag Register SSIF 0 SSIFLAG R W 0 LEGEND R W Read Write R Read only n value after reset Table 16 10 System Software Interrupt Flag Register SSIF Register Field Descriptions Bit Field Type Reset Description 0 SSIFLAG R W 0 This bit represents the system software interrupt flag T...

Page 517: ...d only n value after reset Table 16 11 System Software Interrupt Request Register SSIR Register Field Descriptions Bit Field Type Reset Description 15 8 SSKEY R W 0000 0000 These bits represent the system software interrupt request key These write only bits are executable in both user and privilege modes A 0x75 written to these bits initiates IRQ FIQ interrupts Data in this field is always read as...

Page 518: ... make back doors to permit reprogramming of devices with flash security enabled This section starts with a quick start summary which gives a recipe for best practices for firmware development and for production Next it provides a detailed view of the UCD3138 Flash programming hardware and Boot ROM as a starting point Finally it goes into detail with code examples for the exact procedures for Flash...

Page 519: ...whatever communication port is in use PMBus or serial typically 3 Only program the checksum into a new program version after the backdoors have been tested and verified PMBus backdoors are convenient but unreliable One bug can kill the PMBus function and the backdoor A simple backdoor at the very beginning of the program is much more reliable 17 1 3 Production Setup The best production setup is 1 ...

Page 520: ...s Erase command or many Page Erase commands Erasing the Flash sets all the bits in the Flash to 1 Next the Flash is written to using Write Block commands Then the Flash contents can be verified using Read Block commands Finally an Execute Program command is used to start the Flash program 17 2 3 Clearing the Flash The UCD3138 can erase its own program flash either in pages or as a single block A b...

Page 521: ...strongly suggested The techniques are I O line based backdoors Communications port based backdoors 17 3 3 I O Line Based Backdoors This backdoor can provide security if done properly It starts with the firmware checking an I O line at startup before the rest of the system is initialized and branching to the backdoor if the I O line is in the proper state The big advantage of the I O line based bac...

Page 522: ...g communications port already used in the application Typically this is the PMBus interface but it could be any communications interface The standard TI firmware generally supports a simple communications backdoor with a PMBus D9 command used to clear the flash checksum For added security this could be changed so that it erases the flash instead The command code could be changed In addition more b...

Page 523: ...ero_out_integrity_word Set source address of PFLASH register Uint32 counter for counter 0 counter 500 counter Copy program from PFLASH to RAM program_index source_index register FUNC_PTR func_ptr func_ptr FUNC_PTR 0x19000 Set function to 0x19000 func_ptr func_ptr FUNC_PTR 0x70000 Set function to illegal location func_ptr force reset execute erase checksum return This is the code for actually clear...

Page 524: ...138 training labs void main if GioRegs FAULTIN bit TMS_IN 0 emergency backdoor TMS is normally pulled up by external resistor clear_integrity_word if it s pulled down clear checksum integrity word 17 5 4 I O Line Based Back Door Here is code which actually uses 2 I O lines used in the LLC EVM void main Recommended setting MiscAnalogRegs CLKTRIM bit HFO_LN_FILTER_EN 0 Turn on PMBus address pin curr...

Page 525: ...ced on word boundaries Byte half word and word writes permitted All Registers have read write access in any mode Interrupt Mask and FIQ IRQ Program Control Registers are writeable in privilege mode only A write in user mode to these Registers causes a peripheral illegal access exception Topic Page 18 1 IRQ Index Offset Vector Register IRQIVEC 526 18 2 FIQ Index Offset Vector Register FIQIVEC 527 1...

Page 526: ...RQIVEC Address FFFFFF20 Figure 18 1 IRQ Index Offset Vector Register IRQIVEC 7 0 IRQIVEC R 0 LEGEND R W Read Write R Read only n value after reset Table 18 1 IRQ Index Offset Vector Register IRQIVEC Register Field Descriptions Bit Field Type Reset Description 7 0 IRQIVEC R 0 Index of the IRQ Pending Interrupt Cleared upon read 0 No interrupt pending 1 Pending interrupt on Channel 0 2 Pending inter...

Page 527: ...IQIVEC Address FFFFFF24 Figure 18 2 FIQ Index Offset Vector Register FIQIVEC 7 0 FIQIVEC R 0 LEGEND R W Read Write R Read only n value after reset Table 18 2 FIQ Index Offset Vector Register FIQIVEC Register Field Descriptions Bit Field Type Reset Description 7 0 FIQIVEC R 0 Index of the FIQ pending interrupt Cleared upon read 0 No interrupt pending 1 Pending interrupt on Channel 0 2 Pending inter...

Page 528: ... type Figure 18 3 FIQ IRQ Program Control Register FIRQPR 31 0 FIRQPR R W 0000 0000 0000 0000 0000 0000 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 18 3 FIQ IRQ Program Control Register FIRQPR Register Field Descriptions Bit Field Type Reset Description 31 0 FIRQPR R W 0000 0000 0000 0000 0000 0000 0000 0000 These bits determine whether an interrupt request from a periphe...

Page 529: ...eference 18 4 Pending Interrupt Read Location Register INTREQ Address FFFFFF30 Figure 18 4 Pending Interrupt Read Location Register INTREQ 31 0 INTREQ R 0 LEGEND R W Read Write R Read only n value after reset Table 18 4 Pending Interrupt Read Location Register INTREQ Register Field Descriptions Bit Field Type Reset Description 31 0 INTREQ R 0 Pending Interrupt Requests 0 No interrupt has occurred ...

Page 530: ...K Address FFFFFF34 Figure 18 5 Interrupt Mask Register REQMASK 31 0 REQMASK R W 0000 0000 0000 0000 0000 0000 0000 0000 LEGEND R W Read Write R Read only n value after reset Table 18 5 Interrupt Mask Register REQMASK Register Field Descriptions Bit Field Type Reset Description 31 0 REQMASK R W 0000 0000 0000 0000 0000 0000 0000 0000 Interrupt Request Mask Select 0 Interrupt request channel is disa...

Page 531: ...evision History NOTE Page numbers for previous revisions may differ from page numbers in the current version Changes from Original February 2016 to A Revision Page Global change removed references to DPWM app note 30 Updated Changed document title from UCD3138 Digital Power Peripherals to UCD3138 Digital Power Supply Controller 30 Updated references in Section 2 28 66 ...

Page 532: ...esponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failur...

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