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TR371125 Register Definitions

13

SLWU070D – February 2010 – Revised August 2016

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Copyright © 2010–2016, Texas Instruments Incorporated

TSW6011EVM

5

TR371125 Register Definitions

5.1

Register 1

BB Gain:

The PGA (Programmable Gain Amplifier) setting; range is 0 to 24.

LPFAdj:

Sets the bandwidth of the BB filters. Setting 0 is maximum bandwidth
(~29.6 MHz); setting 254 is minimum
(~ 1.27 MHz). See the

product data sheet

(

SLWS219

) for comprehensive curves.

EN_FastGain:

Enables the fast gain option to adjust PGA gain with external bits.

Gain Select:

Selects whether each bit in the fast gain control is either 1 dB or 2 dB.

3 dB Attn:

Engages the 3-dB attenuator at the baseband output.

Det Filter:

Selects the internal detector filter used in dc offset calibration.

RF Pwd:

Enables SW controlled power down of RF stages inside device.

BUF Pwd:

Enables power down on test buffer for mixer output; default is powered down.

Osc_Test:

Enables dc offset oscillator to the Readback pin.

DC_Off_DIG
Pwd:

Enables SW controlled power down of dc offset correction circuitry.

5.2

Register 2

Auto Cal:

Manual mode allows the dc offset DACs to be user configurable; Auto mode uses
the internally stored values.

En Auto Cal:

When toggled, an Auto Cal is initiated. Note, Auto Cal must be in Auto mode.

I/Q DAC:

Shows the setting of the dc offset I and Q DAC when in Manual mode; range is 0
to 255

Cal Clk Sel:

Toggle between using an externally supplied SPI clock or internal oscillator clock.

Osc. Freq:

Selects the oscillator frequency for the internal clock.

Clk Div:

Sets the clock divider if the control clocks need to be slowed down. Value chosen
in conjunction with Det Filter setting for optimal averaging.

I Det:

Selects the resolution of the I and Q DAC.

5.3

Register 3

I/QLoadA/B:

Selects the mixer gain for the differential BB paths. Typically, these registers do
not need to be modified, but minor I/Q amplitude adjustments are allowed.

Filter Ctrl:

Trims the peaking response of the BB LPF response.

Filter Bypass

Engages the bypass feature of the BB LPF.

5.4

Register 5

Mix GM Trim

No adjustment of this register required

Mix LO Trim

No adjustment of this register required

LO Trim

No adjustment of this register required

Mix Buff Trim

No adjustment of this register required

Filter Trim

No adjustment of this register required

Out Buff Trim

No adjustment of this register required

The hex values in the Register # boxes are the actual values loaded into the TRF371125.

Summary of Contents for TSW6011EVM

Page 1: ...uation module and the abbreviation EVM are synonymous with the TSW6011EVM Contents 1 Overview 2 1 1 EVM Frequency Configuration Options 2 1 2 TSW6011EVM Block Diagram 2 1 3 Digital Processing Block Functions 3 2 Software Installation 5 2 1 Installation Instructions 5 3 EVM Test Configuration 5 3 1 Test Equipment 5 3 2 Calibration 5 4 Board Bring Up 6 4 1 Power Up 6 4 2 Basic RF Test 7 4 3 Software...

Page 2: ... balun to facilitate operation in the desired band The default configuration includes 2 GHz baluns for both inputs Table 1 summarizes the TRF3711xx device frequency options and lists the recommended balun for each device 1 There is considerable overlap in the operating frequency range of the TRF3711xx family of devices Refer to the specific device data sheet and compare performance parameters at t...

Page 3: ...lock Diagram 1 3 Digital Processing Block Functions The FPGA receives the digital data from the ADC and converts it from serial to parallel format The data then are split into two paths One path converts the data back to unsigned serial data and determines which ADC output to route to the LVDS connector The other path either bypasses or goes through the IQ Correction block After IQ Correction proc...

Page 4: ...ebruary 2010 Revised August 2016 Submit Documentation Feedback Copyright 2010 2016 Texas Instruments Incorporated TSW6011EVM The FPGA digital processing block diagram is shown in Figure 2 Figure 2 FPGA Digital Processing Block Diagram ...

Page 5: ...Test Equipment The following equipment is required to operate the TSW6011 Signal generator for input signal Agilent E4438C or equivalent Signal generator for LO signal Agilent E4438C or equivalent Spectrum analyzer Agilent E4440A or equivalent Programming computer USB cable provided RF cables 3 2 Calibration The RF cables must be good quality because of the high frequency signals Measure the inser...

Page 6: ...r the CDCE62005 SJP5 Open used to select source for LNA U8 GAIN_SEL input SJP6 Pins 2 and 3 selects CDCE62005 power down source SJP7 Pins 1 and 2 disables CDCE62005 AUX_IN source Y4 SJP8 Pins 1 and 2 selects DAC5672 SLEEP input source SJP9 Pins 1 and 2 selects USB to parallel interface device power source SJP10 Pins 2 and 3 selects DAC5672 input clock source Note that the following LE s are now il...

Page 7: ...dB for input balun and transmission line losses Step 2 Since the board default configuration bypasses the two LNAs inject an RF signal at J1 at 2153 MHz at 15 dBm Compensate for cable loss including about 1 dB for input transmission line losses and balun Step 3 Connect a spectrum analyzer to J6 Step 4 Set up the spectrum analyzer as follows Set span to 20 MHz Set center frequency to 30 72 MHz Set ...

Page 8: ...ght 2010 2016 Texas Instruments Incorporated TSW6011EVM 4 3 Software Operation When the GUI first starts the front control panel appears as shown in Figure 4 Figure 4 TSW6011EVM Software GUI Front Panel To enable the GUI the user must click on the button labeled Connect in the upper left hand corner If communication between the GUI and TSW6011 is successful the button changes to display Disconnect...

Page 9: ...ls 1 and 2 The TR371125 outputs are routed to channels 5 and 6 Channels 3 4 7 and 8 are not used The following sequence is performed every time this GUI window is opened Reset the device Power up ADC Channels 1 2 5 and 6 Power down ADC channels 3 4 7 and 8 Set the serial output stream to send MSB first Set the data format to twos complement Set the input clock to differential mode To power down an...

Page 10: ...the TR371125 is initialized by the software automatically The default settings are those shown in the control panel when it opens Every time this panel is opened the default values are loaded This process is reported by the message in red DEFAULTS RE LOADED as shown in Figure 7 Click on the BB Gain field and set the gain to 5 Click the Filter Bypass checkbox to bypass the TR371125 LPF internal fil...

Page 11: ... A Enable When selected places LNA U2 into low gain mode 3 dB typ When not selected the LNA is in high gain mode 14 5 dB typ LNA B Enable When selected places LNA U8 into low gain mode 3 dB typ When not selected the LNA is in high gain mode 14 5 dB typ DAC Data Enable When selected enables data through digital processing path to be routed to the DAC When disabled no data are routed to the DAC DAC ...

Page 12: ... is enabled When disabled the DC offset compensation block is bypassed IQ Correction Tap Shift Avg Initial value is 13 which is coarse adaption Users can choose the value of 18 which slows the adaption algorithm Manual Tap Shift This option is not recommended however it allows selection of a tap shift value ranging from 10 to 18 The tap shift value is automatically chosen inside the FPGA firmware ...

Page 13: ...et DACs to be user configurable Auto mode uses the internally stored values En Auto Cal When toggled an Auto Cal is initiated Note Auto Cal must be in Auto mode I Q DAC Shows the setting of the dc offset I and Q DAC when in Manual mode range is 0 to 255 Cal Clk Sel Toggle between using an externally supplied SPI clock or internal oscillator clock Osc Freq Selects the oscillator frequency for the i...

Page 14: ...scription J1 RF input Bypasses both LNAs J2 RF input to LNA 2 Bypasses LNA 1 J3 RF input to LNA 1 J4 TR371125 LO input source J13 ADC 1 analog input Positive analog input when T4 is bypassed J14 ADC 1 negative analog input when T4 is bypassed J16 ADC 2 analog input Positive analog input when T5 is bypassed J17 ADC 2 negative analog input when T5 is bypassed J8 External reference for CDCE62005 J5 S...

Page 15: ...or power Set to 1 2 to power down oscillator 2 3 to power up 1 2 SJP4 CDCE62005 primary reference enable Set to 1 2 to power down oscillator 2 3 to power up 2 3 SJP6 CDCE62005 power down Set to 2 3 to enable CDC set to 1 2 for FPGA control of power down mode 2 3 SJP10 DAC5672 clock source Set to 1 2 for CDCE62005 set to 2 3 for FPGA source 2 3 SJP8 DAC5672 sleep mode Set to 1 2 for FPGA control se...

Page 16: ...m the list following Figure 9 11 Added 4 values in the control panel 11 Deleted Section 6 Optional Configurations 13 Deleted LED definitions D8 D2 D9 in Section A 1 14 Changed D4 definition in Section A 1 14 Added D5 IQ correction enabled with blinking in Section A 1 14 Revision History Changes from B Revision June 2010 to C Revision Page Changed the first two sentences of second paragraph in Sect...

Page 17: ...ring the warranty period to the address designated by TI and that are determined by TI not to conform to such warranty If TI elects to repair or replace such EVM TI shall have a reasonable time to repair such EVM or provide replacements Repaired EVMs shall be warranted for the remainder of the original warranty period Replaced EVMs shall be warranted for a new full ninety 90 day warranty period 3 ...

Page 18: ... by Industry Canada to operate with the antenna types listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated Antenna types not included in this list having a gain greater than the maximum gain indicated for that type are strictly prohibited for use with this device Concernant les EVMs avec antennes détachables Conformément à la rég...

Page 19: ... connecting any load to the EVM output If there is uncertainty as to the load specification please contact a TI field representative During normal operation even with the inputs and outputs kept within the specified allowable ranges some circuit components may have elevated case temperatures These components include but are not limited to linear regulators switching transistors pass transistors cu...

Page 20: ...F REMOVAL OR REINSTALLATION ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES RETESTING OUTSIDE COMPUTER TIME LABOR COSTS LOSS OF GOODWILL LOSS OF PROFITS LOSS OF SAVINGS LOSS OF USE LOSS OF DATA OR BUSINESS INTERRUPTION NO CLAIM SUIT OR ACTION SHALL BE BROUGHT AGAINST TI MORE THAN ONE YEAR AFTER THE RELATED CAUSE OF ACTION HAS OCCURRED 8 2 Specific Limitations IN NO EVENT SHALL T...

Page 21: ...esponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failur...

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