Optional Features and Configurations
10
SLAU454A – July 2012 – Revised April 2016
Copyright © 2012–2016, Texas Instruments Incorporated
Revision History
5
Optional Features and Configurations
5.1
Clocking
The EVM board comes with the LMK04806 device which has an internal VCO frequency range of
2370–2600 MHz. If the desired clock is not derived from this frequency range using integer dividers, then
swap this device out for another LMK04800 with a different VCO range. Determine which LMK04800
works for the desired frequency range by consulting the LMK04800 data sheet (
).
Set up the LMK04800 in clock distribution mode or as a clock generator using single or dual PLL mode.
The different modes of operation are listed below.
1.
External Clock Mode:
Setting up the LMK4806 in clock distribution mode permits the use of an
external clock source. This allows for coherent sampling by providing a clock that is synchronized to
the other signal sources. The TSW4806 GUI includes a configuration file for the external clock mode.
This file is located in the GUI installation directory in the folder
Configuration Files
and is named
external_clock.txt
. Load the file by clicking the
Load
button, navigating to the correct folder, selecting
the file, and clicking
OK
. Provide an external clock through the
CLKIN1
SMA J12 connector on the
TSW4806 board.
2.
On-board Clock using Single PLL Mode:
This is the default mode of operation for the TSW4806.
The 10-MHz on-board oscillator acts as the reference for the PLL and the divided down internal VCO
acts as the clock source. All of the factory provided configurations stored in the EEPROM and the
provided files in the
Configuration Files
folder not mentioned elsewhere in this document operate in
this mode. Use an external reference (2 Vp-p min) in place of the on-board oscillator. Operate in this
mode by providing a clock source to SMA J11, and moving the shunt on jumper JP5 to pins 2-3. The
10-MHz oscillator is now disabled by moving the shunt on jumper JP4 to pins 2-3.
3.
On-board Clock using Dual PLL Mode:
In this mode of operation, providing a low-frequency
reference generates a synchronized sampling clock at a higher frequency. The reference comes from
any source, such as a 10-MHz reference from a piece of test equipment, this allows synchronization
between all signal sources and is used for coherent sampling. Installing a VCXO at Y2 allows the use
of this mode. Update the loop filters if there is a change in reference or VCXO. Use the Clock Design
Tool (
http://www.ti.com/tool/clockdesigntool
) for designing the loop filters and PLL settings based on
the reference, VCXO, and output frequencies.
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (July 2012) to A Revision
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Page
•
Made changes to step 1 and 3 in the
Hardware Setup
section.
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