Functionality
5
SLWU092 – April 2017
Copyright © 2017, Texas Instruments Incorporated
TSW14J57 JESD204B High-Speed Data Capture and Pattern Generator
Card User's Guide
2.1
ADC EVM Data Capture
New TI high-speed ADCs and DACs now have high-speed serial data that meets the JESD204B standard.
These devices are generally available on an EVM that connects directly to the TSW14J57EVM. The
common connector between the EVMs and the TSW14J57EVM is a Samtec high-speed, high-density
FMC+ connector (ASP-184329-01) suitable for high-speed differential pairs up to 28 Gbps. A common
pinout for the connector across a family of EVMs has been established. At present, the interface between
the EVMs and the TSW14J57EVM has defined connections for 29 spare differential LVDS or 58 single-
ended CMOS signals, 16 lanes of serial differential data, two device clock pairs, two JESD204B SYSREF
and SYNC pairs. The board has a spare SMA interface to the FPGA, 4 spare dip switches, a pushbutton
switch, several spare test points routed to the FPGA and 8 status LEDs.
The data format for JESD204B ADCs and DACs is a serialized format, where individual bits of the data
are presented on the serial pairs commonly referred to as lanes. Devices designed around the JESD204B
spec can have up to 8 lanes for transmitting or receiving data. The firmware in the FPGA on the
TSW14J57 is designed to accommodate any of TI's ADC or DAC operating with any number of lanes from
1 to 16.
The GUI loads the FPGA with the appropriate firmware and a specific JESD204B configuration, based on
the ADC device selected in the device drop down window. Each ADC device that appears in this window
has an initialization file (.ini) associated to it. This .ini file contains JESD information, such as number of
lanes, number of converters, octets per frame, and other parameters. This information is loaded into the
FPGA registers after the user clicks on the capture button. After the parameters are loaded,
synchronization is established between the data converter and FPGA and valid data is then captured into
the on-board memory. See the
High-Speed Data Capture Pro GUI Software User's Guide
(
under the Technical Documents section and section 2.3 in the guide for more information. Several .ini files
are available to allow the user to load pre-determined ADC JESD204B interfaces. For example, if the user
selects the ADC called "ADS42JB69_LMF_421", the FPGA will be configured to capture data from the
ADS42JB69EVM with the ADC JESD interface configured for 4 lanes, 2 converters, and 1 octet per frame.
The TSW14J57 device can capture up to 1G 16-bit samples at a maximum line rate of 15 Gbps that are
stored inside the on-board DDR4 memory. To acquire data on a host PC, the FPGA reads the data from
memory and transmits parallel data to the on-board high-speed parallel-to-USB converter.
2.2
DAC EVM Pattern Generator
In pattern generator mode, the TSW14J57EVM generates desired test patterns for DAC EVMs under test.
These patterns are sent from the host PC over the USB interface to the TSW14J57. The FPGA stores the
data received into the on-board DDR4 memory. The data from the memory is then read by the FPGA,
converted to JESD204B serial format, then transmitted to a DAC EVM. The TSW14J57 can generate
patterns up to 1G 16-bit samples at a line rate up to 15 Gbps.
The GUI comes with several existing test patterns that can be download immediately. The GUI also has a
pattern generation tool that allows the user to generate a custom pattern, then download it to the on-board
memory. See the
High-Speed Data Capture Pro Software User's Guide
(
) for more information.
Like the ADC capture mode, the DAC pattern generator mode uses .ini files to load predetermined
JESD204B interface information to the FPGA.
3
Hardware Configuration
This section describes the various portions of the TSW14J57EVM hardware.
3.1
Power Connections
The TSW14J57EVM hardware is designed to operate from a single supply voltage of +12 V DC. The
power input is controlled by the on and off switch, SW3. Make sure this switch is in the off position before
inserting the provided power cable. Insert the connector end of the power cable into J16 of the EVM.
Connect the positive red wire end of the power cable to +12 V DC output of a power supply rated for at
least 2 Amps. Connect the negative black wire to the RETURN or GND of the power supply. The board
can also be powered up by pro12 V DC to the red test point, TP38, and the return to any black
GND test point. As an example, the TSW14J57 draws approximately 0.6 A at power-up and 1.4 A when
capturing 4 lanes of data from an ADC34J45 at a line rate of 3.2 Gpbs.
