Texas Instruments TSW12QJ1600, User Manual

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19 SLAU796 – July 2020
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HSDC Pro Settings for Optional ADC Device Configuration
Appendix B
SLAU796 – July 2020
HSDC Pro Settings for Optional ADC Device Configuration
This appendix provides settings for optional ADC device configuration in HSDC Pro.
B.1 Changing the Number of Frames per Multi-Frame (K)
Changing the number of frames per multi-frame output by the JESD204 transmitter (ADC device) is
configured using the K parameter( when using modes with 8B/10B encoding) on the
JESD204C tab in the
Configuration GUI. This parameter must be matched by the receiving device, and the SYSREF frequency
must also be programmed to a compatible frequency. Ensure that the K value complies with the K Min
and Step values for the selected JMODE. Refer to the TSW12QJ1600 operating modes table in the device
datasheet..
B.2 Customizing the EVM for Optional Clocking Support
The TSW12QJ1600EVM can be clocked using two different methods:
1. Onboard 50M ref to ADC PLL clocking option
2. Ext Ref to ADC PLL clocking
B.2.1 Onboard 50M Ref to ADC PLL (Default)
The 50-MHz onboard crystal oscillator is use provide reference signal to ADC's single-ended clock input.
The ADC PLL generate a sampling clock for the ADC from this 50 MHz. In this clocking mode, the ADC
also generates the reference clock signal for FPGA. FPGA takes this reference clock and generates the
SYSREF signal for the ADC and feeds it back to the ADC.
Figure B-1 shows the block diagram of the
Onboard 50M Ref to ADC PLL clocking option:
No hardware change is need to use this mode.