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10.9 Pin Strapping

Use the

Pin Strapping

) to aid in selection of external pin strapping resistors used to program

some of the PMBus commands at power up. The

EEPROM Value

column shows the values currently configured

to the related PMBus commands.

Figure 10-9. Configure – Pin Strapping

Using the Fusion GUI

SLUUCK6 – DECEMBER 2021

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TPSM8D6C24EVM-2V0 User's Guide

31

Copyright © 2021 Texas Instruments Incorporated

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Summary of Contents for TPSM8D6C24EVM-2V0

Page 1: ...ent Procedure 9 6 2 Efficiency Measurement Test Points 9 6 3 Control Loop Gain and Phase Measurement Procedure 10 7 Performance Data and Typical Characteristic Curves 11 7 1 Efficiency 11 7 2 Load Reg...

Page 2: ...M8D6C24EVM 2V0 Internal Layer 4 Top View 17 Figure 8 8 TPSM8D6C24EVM 2V0 Internal Layer 5 Top View 17 Figure 8 9 TPSM8D6C24EVM 2V0 Internal Layer 6 Top View 18 Figure 8 10 TPSM8D6C24EVM 2V0 Internal B...

Page 3: ...aces or sharp edges Do not reach under the board during operation CAUTION The circuit module may be damaged by over temperature To avoid damage monitor the temperature during evaluation and provide co...

Page 4: ...3 and JP4 in UVLO position 3 50 V Output Characteristics VOUT_A output voltage VOUTA 0 8 V VOUT_B output voltage VOUTB 1 2 V VOUT_A output load current IOUTA 0 35 A VOUT_B output load current IOUTB 0...

Page 5: ...F C6 22uF C2 100uF C1 22uF C3 PVIN PGND PGND PVIN_A PVIN_A PGND AGND_A AVIN_A PGND 22uF C13 22uF C12 6800pF C14 22uF C10 100uF C9 22uF C11 PVIN PGND PGND PVIN_B PGND PGND AGND_B AVIN_B PVIN_B CLK DATA...

Page 6: ...ge Source The input voltage source VIN must be a 0 V to 18 V variable DC source capable of supplying a minimum of 8 ADC to support 35 A load with 5 V input or 16 ADC to support a combined 70 A load Co...

Page 7: ...point Sensitive signal TP13 VSHARE_B VSHARE_B measurement point Sensitive signal TP14 PGood_B PGOOD signal of VOUT_B TP15 SYNC External clock input SYNC IN or output to synchronize other devices SYNC...

Page 8: ...5 VOUT_A VOUT connector T6 T8 PGND VOUT connector 4 4 Evaluating Split Rail Input The default configuration of the EVM is for single rail input Split rail input enables operation with 3 3 V PVIN For s...

Page 9: ...and inductor it is important to measure the voltages at the correct location This is necessary because otherwise the measurements will include losses that are not related to the power train itself Lo...

Page 10: ...esulting output of VOUT_A Bode can be measured by a network analyzer with a CH_B CH_A configuratio n VOUT_B TP19 CHA_VoutB Input to feedback divider of VOUT_B The amplitude of the perturbation at this...

Page 11: ...803 0 8035 0 804 0 8045 0 805 PVIN 5 V PVIN 12 V PVIN 16 V Figure 7 3 VOUT_A Load Regulation Output Current A Output Voltage V 0 5 10 15 20 25 30 35 1 2 1 2005 1 201 1 2015 1 202 1 2025 1 203 1 2035...

Page 12: ...nsient Response Figure 7 8 VOUT_B Transient Response 7 5 Control Loop Bode Plot Figure 7 9 VOUT_A Bode Plot 35 A Load Figure 7 10 VOUT_B Bode Plot 35 A Load Performance Data and Typical Characteristic...

Page 13: ...pple No Load Figure 7 12 VOUT_B Output Ripple No Load Figure 7 13 VOUT_A Output Ripple 35 A Load Figure 7 14 VOUT_B Output Ripple 35 A Load www ti com Performance Data and Typical Characteristic Curve...

Page 14: ...5 A CC Load 7 8 Control Off Figure 7 17 and Figure 7 18 illustrate the control off waveforms at 35 A outputs Figure 7 17 VOUT_A Shutdown From Control 35 A CC Load Figure 7 18 VOUT_B Shutdown From Cont...

Page 15: ...N 12 V IOUTA 35 A IOUTB 35A Airflow 200 LFM 10 minute soak Figure 7 19 Thermal Image www ti com Performance Data and Typical Characteristic Curves SLUUCK6 DECEMBER 2021 Submit Document Feedback TPSM8D...

Page 16: ...Component View Top View Figure 8 2 TPSM8D6C24EVM 2V0 Bottom Side Component View Bottom View Figure 8 3 TPSM8D6C24EVM 2V0 Top Copper Top View Figure 8 4 TPSM8D6C24EVM 2V0 Internal Layer 1 Top View EVM...

Page 17: ...r 3 Top View Figure 8 7 TPSM8D6C24EVM 2V0 Internal Layer 4 Top View Figure 8 8 TPSM8D6C24EVM 2V0 Internal Layer 5 Top View www ti com EVM Assembly Drawing and PCB Layout SLUUCK6 DECEMBER 2021 Submit D...

Page 18: ...Top View Figure 8 10 TPSM8D6C24EVM 2V0 Internal Bottom Layer Top View EVM Assembly Drawing and PCB Layout www ti com 18 TPSM8D6C24EVM 2V0 User s Guide SLUUCK6 DECEMBER 2021 Submit Document Feedback C...

Page 19: ...AP CERM 47 F 10 V 10 X7R 1210 1210 GRM32ER71A476KE15L MuRata C23 C42 2 100 pF CAP CERM 100 pF 50 V 10 X7R 0402 402 8 85012E 11 Wurth Elektronik C24 C25 C46 C47 4 10 F CAP CERM 10 F 10 V 20 X7R 0603 60...

Page 20: ...1 W AEC Q200 Grade 0 0603 603 CRCW060310R0JNEA Vishay Dale R2 R6 2 30 1 k RES 30 1 k 1 0 1 W 0603 603 RC0603FR 0730K1L Yageo R4 R8 2 11 0 k RES 11 0 k 1 0 1 W 0603 603 RC0603FR 0711KL Yageo R7 R14 R36...

Page 21: ...Testpoint 5010 Keystone TP2 TP3 TP4 TP10 TP16 TP22 TP27 7 Test Point Multipurpose Black TH Black Multipurpose Testpoint 5011 Keystone TP5 TP7 TP8 TP9 TP11 TP12 TP13 TP14 TP15 TP17 TP19 TP20 TP21 TP23...

Page 22: ...R28 0 10 0 k RES 10 0 k 1 0 1 W 0603 603 RCG060310K0FKEA Vishay Draloric R18 R30 0 53 6 k RES 53 6 k 1 0 1 W AEC Q200 Grade 0 0603 603 CRCW060353K6FKEA Vishay Dale R26 0 0 RES 0 5 0 1 W AEC Q200 Grad...

Page 23: ...to find TPSM8D6C24 The EVM needs power to be recognized by the Fusion GUI See Section 5 for the recommended procedure Figure 10 1 Select Device Scanning Mode www ti com Using the Fusion GUI SLUUCK6 DE...

Page 24: ...r device and the loop follower device are tied to same bus interface In a two phase stacking system the loop controller device will receive and respond to all PMBus communication and loop follower dev...

Page 25: ...Figure 10 3 Configure ON_OFF_CONFIG www ti com Using the Fusion GUI SLUUCK6 DECEMBER 2021 Submit Document Feedback TPSM8D6C24EVM 2V0 User s Guide 25 Copyright 2021 Texas Instruments Incorporated...

Page 26: ...Compensation Vout Mode and Vout Scale Loop To change these settings to a new value click on Stop Power Conversion then Close and continue The GUI will automatically disable conversion write the new va...

Page 27: ...ed are found and configured on the SMBALERT Mask tab Figure 10 5 Figure 10 5 Configure SMBALERT Mask www ti com Using the Fusion GUI SLUUCK6 DECEMBER 2021 Submit Document Feedback TPSM8D6C24EVM 2V0 Us...

Page 28: ...cale Loop Vout Transition Rate and Iout Cal Offset are found on the Device Info tab see Figure 10 6 Figure 10 6 Configure Device Info Using the Fusion GUI www ti com 28 TPSM8D6C24EVM 2V0 User s Guide...

Page 29: ...b see Figure 10 7 to calibrate the IOUT Temp of each phase Figure 10 7 Phase Commands www ti com Using the Fusion GUI SLUUCK6 DECEMBER 2021 Submit Document Feedback TPSM8D6C24EVM 2V0 User s Guide 29 C...

Page 30: ...the configurable parameters which also shows other details like Hex encoding Figure 10 8 Configure All Config Using the Fusion GUI www ti com 30 TPSM8D6C24EVM 2V0 User s Guide SLUUCK6 DECEMBER 2021 S...

Page 31: ...m some of the PMBus commands at power up The EEPROM Value column shows the values currently configured to the related PMBus commands Figure 10 9 Configure Pin Strapping www ti com Using the Fusion GUI...

Page 32: ...data Quick access to On Off Config Control pin activation and OPERATION command Margin control Clear Fault Selecting Clear Faults clears any prior fault flags With two devices stacked together the Io...

Page 33: ...er left corner Figure 10 11 shows the status of the device Figure 10 11 Status Screen www ti com Using the Fusion GUI SLUUCK6 DECEMBER 2021 Submit Document Feedback TPSM8D6C24EVM 2V0 User s Guide 33 C...

Page 34: ...ther than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control tec...

Page 35: ...These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not in...

Page 36: ...instructions set forth by Radio Law of Japan which includes but is not limited to the instructions below with respect to EVMs which for the avoidance of doubt are stated strictly for convenience and s...

Page 37: ...any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electr...

Page 38: ...R DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthe...

Page 39: ...change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of thes...

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