3 Schematic
1
2
3
4
5
6
7
8
9
10
J2
P MBus
PMBus
PGND
Gre e n
2
1
LED1
1.00k
R42
47uF
C33
47uF
C29
47uF
C34
47uF
C35
47uF
C31
47uF
C30
47uF
C32
47uF
C26
47uF
C36
47uF
C20
47uF
C27
47uF
C28
PGND
VOUT
47uF
C55
47uF
C51
47uF
C56
47uF
C57
47uF
C53
47uF
C52
47uF
C54
47uF
C48
47uF
C58
47uF
C59
47uF
C49
47uF
C50
PGND
VOUT
VOUT
VOS NS_A
TP 1
PVIN
TP 8
CHB_Vout
TP 2
PGND
100uF
C8
100uF
C7
PGND
TP 7
CHA_Vout
1
2
T4
AVIN
PGND
PGND
Bode_Input
TP 24
CLK
TP 23
CNTL
TP 26
DATA
TP 25
S MBALRT
1
2
S MB1
VOUT
TP 16
PGND
TP 4
PGND
PGND
1
2
T1
PVIN
1
2
T2
PGND
47uF
C15
47uF
C16
47uF
C17
47uF
C18
47uF
C19
47uF
C37
47uF
C63
47uF
C64
47uF
C65
47uF
C66
47uF
C67
47uF
C68
47uF
C21
47uF
C22
47uF
C69
47uF
C70
PGND
VOUT
TP 5
Re mote S e ns e Vout (+)
TP 9
Re mote S e ns e Vout (-)
VOUT
S MBALT
CLK
DATA
CNTL
PGND
1
2
J P8
P MBus to AVIN
VBUS
1
D-
2
D+
3
ID
4
GND
5
6
7
8
11
10
9
J1
Micro-USB P owe r
PGND
1
2
J P7
USB to P VIN
PVIN
PVIN
30V
D1
30V
D2
HW1
BS R193A_Ha rdwa re .SchDoc
Input: 2.95 V to 16 V
Output: 0.5 V to 3.6 V at 70 A
PGND
SYNC
29
EN_B
25
SMB_ALRT_A
6
P GND
1
AGND_A
21
P GND
4
AGND_B
27
P VIN_A
18
AVIN_A
20
PMB_DATA_A
8
P VIN_A
55
P VIN_B
24
P VIN_B
56
PMB_CLK_A
7
VOSNS_A
2
VOUT_A
50
VOUT_A
51
P GND
52
BCX_CLK_A
11
S W_A
53
P GND
17
P GND
23
P GND
43
S W_B
58
VOUT_B
47
VOUT_B
48
P GND
49
AVIN_B
26
VOSNS_B
45
P GND
46
P GD/RS T_A
9
P GND
30
EN_A
19
PMB_DATA_B
39
PMB_CLK_B
40
SMB_ALRT_B
41
BCX_DATA_A
10
BCX_CLK_B
36
P GD/RS T_B
38
BCX_DATA_B
37
P GND
54
P GND
57
P GND
59
VDD5_A
22
BP1V5_A
5
VSEL_A
15
ADRSEL_A
14
MSEL1_A
13
VSHARE_A
12
MSEL2_A
16
VDD5_B
28
GOSNS /FLWR_A
3
BP1V5_B
42
GOSNS /FLWR_B
44
VSHARE_B
35
MSEL2_B
31
VSEL_B
32
ADRSEL_B
33
MSEL1_B
34
U1
TP S M8D6x24MOW59
AVIN_B
ADRSEL_A
MSEL2_A
VSEL_A
53.6k
R18
MSEL1_A
14.7k
R22
14.7k
R24
0
R21
22uF
C5
22uF
C4
6800pF
C6
22uF
C2
100uF
C1
22uF
C3
PVIN
PGND
PGND
P VIN_A
P VIN_A
PGND
AGND_A
AVIN_A
PGND
22uF
C13
22uF
C12
6800pF
C14
22uF
C10
100uF
C9
22uF
C11
PVIN
PGND
PGND
P VIN_B
PGND
PGND
AGND_B
AVIN_B
P VIN_B
CLK
DATA
DATA
CLK
S MBALT
S MBALT
PGND
0.1uF
C41
P VIN_A
30.1k
R2
PGND
1
2
3
4
5
6
J P3
EN_A
EN_A
VOS NS_A
S W_A
VOUT
GOS NS_A
10
R3
10
R1
1
2
3
J P2
AVIN_B
1
2
3
J P1
AVIN_A
AVIN_A
0
R26
VS HARE_A
VS HARE_A
ADRSEL_B
MSEL2_B
VSEL_B
53.6k
R30
MSEL1_B
14.7k
R35
0
R32
TP 6
VOUT
TP 10
PGND
S W_B
VOS NS_B
VOUT
GOS NS_B
BP1V5_A
VDD5_A
EN_B
PGND
0.1uF
C43
P VIN_B
30.1k
R6
1
2
3
4
5
6
J P4
EN_B
PGND
BP1V5_B
VDD5_B
VSEL_A = 0.8V Output
0
R19
TP 15
SYNC
SYNC
0
R20
BCX_CLK_A
BCX_CLK_B
BCX_DATA_A
BCX_DATA_B
P GD_A
P GD_B
0.022uF
C44
0.022uF
C45
VS HARE_B
BCX_CLK_B
BCX_DATA_B
10.0k
R31
10.0k
R25
VDD5_A
VDD5_B
1
2
J P5
VDD5_A
BP1V5_A
BP1V5_B
AGND_A
AGND_B
TP 12
VS HARE_A
TP 13
VS HARE_B
PGND
VDD5_A
1
2
J P6
VDD5_B
PGND
VDD5_B
TP11
PGood_A
TP 14
PGood_B
AVIN
VOUT
VOS NS_B
TP 20
CHB_VoutB
TP 19
CHA_VoutB
PGND
Bode_Input
1
2
S MB2
VOUT_B
TP 17
Re mote S e ns e Vout B (+)
TP 21
Re mote S e ns e Vout B (-)
TP 18
VOUT_B
TP 22
PGND
0.022uF
C71
0.022uF
C72
1
2
T5
VOUT
1
2
T6
PGND
TP 27
PGND
PGND
100pF
C42
100pF
C23
1
2
T7
VOUT
1
2
T8
PGND
470uF
C39
470uF
C40
470uF
C61
470uF
C62
10
µ
F
C25
10
µ
F
C24
10
µ
F
C47
10
µ
F
C46
47uF
C38
47uF
C60
PVIN
11.0k
R4
11.0k
R8
1
2
T3
PGND
AVIN
GOS NS_A
GOS NS_B
BP1V5_A
BP1V5_B
NT1
Ne t-Tie
NT2
Ne t-Tie
NT4
Ne t-Tie
NT3
Ne t-Tie
49.9
R9
49.9
R12
49.9
R10
49.9
R13
10.0
R7
10.0
R14
49.9
R37
49.9
R39
49.9
R38
49.9
R40
10.0
R36
10.0
R41
10.0k
R5
10.0k
R11
CNTL
CNTL
68.1k
R33
10.0k
R27
10.0k
R28
10.0k
R17
10.0k
R16
10.0k
R15
10.0k
R23
26.1k
R29
26.1k
R34
SW_A and SW_B have a via test point on the bottom of the PCB
TP 3
PGND
Figure 3-1. TPSM8D6C24EVM-2PH Schematic
Schematic
SLUUCL8A – DECEMBER 2021 – REVISED FEBRUARY 2022
TPSM8D6C24 2-Phase Power Module Evaluation Module User's Guide
5
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