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36

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J8

DNP

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5

6

4

2

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9

1

0

8

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2

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1

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0

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9

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0

2

9

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1

3

4

3

3

3

6

3

5

3

8

3

7

4

0

3

9

4

1

4

2

J10

DNP

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6

4

2

7
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J7

DNP

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2

7

9

1

0

8

1

2

1

1

1

4

1

3

1

6

1

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1

7

2

0

1

9

2

2

2

1

2

4

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3

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6

2

5

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8

2

7

3

0

2

9

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2

3

1

3

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3

3

3

6

3

5

3

8

3

7

4

0

3

9

4

1

4

2

J9

DNP

DIO_6B

DIO_7B

PXIe-4112 (CH#1)

PXIe-4112 (CH#1) S+

PXIe-4112 (CH#1) S-

AGND

AGND

0

R109

0

R111

0

R108

DNP

0

R110

DNP

Bottom Side Pogos

PXIe-4139-1 F+

AGND

AGND

EGND

PXIe-4139-1 S+

PXIe-4139-1 S-

PXIe-5162_CH0

PXIe-5162_CH1

PXIe-5162_CH2

PXIe-5162_CH3

PXIe-5110_CH0

PXIe-5110_CH1

PXIe-4145 (CH#0) F+

PXIe-4145 (CH#0) S+

PXIe-4145 (CH#0) S-

PXIe-4145 (CH#1) F+

PXIe-4145 (CH#1) S+

PXIe-4145 (CH#1) S-

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3

5

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4

2

7

9

1

0

8

1

2

1

1

1

4

1

3

1

6

1

5

1

8

1

7

2

0

1

9

2

2

2

1

2

4

2

3

2

6

2

5

2

8

2

7

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0

2

9

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2

3

1

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3

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3

5

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8

3

7

4

0

3

9

4

1

4

2

J

J10

D

D

DN

N

NP

P

P

Bottom Side Pogos

PXIe-4139-1 F+

AGND

AGND

EGND

PX

P

P Ie-4

X

X

139-1 S+

PX

P

P Ie-4

X

X

139-1 S-

PXIe-5162_CH0

PXIe-5162_CH1

PXIe-5162_CH2

PXIe-5162_CH3

PXIe-5110_CH0

PXIe-5110_CH1

PXIe-4145 (CH#0) F+

PX

P

P Ie-4

X

X

145 (C

45

H#

H

H 0) S+

PX

P

P Ie-4

X

X

145 (C

45

H#

H

H 0) S-

PXIe-4145 (CH#1) F+

PX

P

P Ie-4

X

X

145 (C

45

H#

H

H 1) S+

PX

P

P Ie-4

X

X

145 (C

45

H#

H

H 1) S-

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J8

D

D

D

DN

N

NP

P

P

DIO_6B

DIO_7B

0

R109

0

R111

Left Side Pogos

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3
5

6

4

2

7
9

10

8

12

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13

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39

41

42

J7

D

D

D

DN

N

NP

P

P

0

R108

D

D

D

D

D

DN

N

N

N

N

NP

P

P

P

P

0

R110

D

D

D

D

D

DN

N

N

N

N

NP

P

P

P

P

Right Side Pogos

E36311A-1 (+6V)

DMM_Site1_1

DMM_Site1_2

DMM_Site1_3

AWG_CH1_to_SIte1

PXIe-5172-1_CH1_Site1

PXIe-5172-1_CH3_Site1

PXIe-5172-1_CH5_Site1

PXIe-5172-1_CH7_Site1

PXIe-5172-2_CH1_Site1

PXIe-5172-2_CH3_Site1

PXIe-5172-2_CH5_Site1

PXIe-5172-2_CH7_Site1

DMM_Site1_4

DMM_Site1_5

AWG_CH2_to_SIte1

PXIe-5172-1_CH0_Site1

PXIe-5172-1_CH2_Site1

PXIe-5172-1_CH4_Site1

PXIe-5172-1_CH6_Site1

PXIe-5172-2_CH0_Site1

PXIe-5172-2_CH2_Site1

PXIe-5172-2_CH4_Site1

PXIe-5172-2_CH6_Site1

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6

4

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9

1

0

8

1

2

1

1

1

4

1

3

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8

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0

1

9

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2

2

1

2

4

2

3

2

6

2

5

2

8

2

7

3

0

2

9

3

2

3

1

3

4

3

3

3

6

3

5

3

8

3

7

4

0

3

9

4

1

4

2

J

J9

D

D

DN

N

N

N

NP

P

P

PXIe-4112 (CH#1)

PX

P

P Ie-4

X

X

112 (C

12

H#

H

H 1) S+

PX

P

P Ie-4

X

X

112 (C

12

H#

H

H 1) S-

AGND

AGND

DMM_Site1_1

DMM_Site1_2

DMM_Site1_3

AW

A

A

G_CH1_to_

_

SIte1

PXIe-5172-1_CH1_Site1

PXIe-5172-1_CH3_Site1

PXIe-5172-1_CH5_Site1

PXIe-5172-1_CH7_Site1

PXIe-5172-2_CH1_Site1

PXIe-5172-2_CH3_Site1

PXIe-5172-2_CH5_Site1

PXIe-5172-2_CH7_Site1

DMM_Site1_4

DMM_Site1_5

AW

A

A

G_CH2_to_

_

SIte1

PXIe-5172-1_CH0_Site1

PXIe-5172-1_CH2_Site1

PXIe-5172-1_CH4_Site1

PXIe-5172-1_CH6_Site1

PXIe-5172-2_CH0_Site1

PXIe-5172-2_CH2_Site1

PXIe-5172-2_CH4_Site1

PXIe-5172-2_CH6_Site1

Upper Side Pogos

E36311A-1 (+25V)

PXIe-5922_CH0_Site1

PXIe-5922_CH1_Site1

PXIe-4113 (CH#1) F+

PXIe-4113 (CH#1) S+

PXIe-4113 (CH#1) S-

PGND

PGND

AGND

EGND

PGND

AGND

EGND

Local Star GND Connection

0

R112

DNP

0

R114

DNP

0

R113

DNP

0

R115

DNP

0

R117

DNP

0

R116

DNP

PXIe-4137 S-

PXIe-4137 S+

PXIe-4137 F+

Label Assembly Note

ZZ1

This Assembly Note is for PCB labels only

Assembly Note

ZZ2

These assemblies are ESD sensitive, ESD precautions

shall be observed.

Assembly Note

ZZ3

These assemblies must be clean and free from flux a nd all contaminants. Use of no clean flux is not ac ceptable.

Assembly Note

ZZ4

These assemblies must comply with workmanship stand ards IPC-A-610 Class 2, unless otherwise specified.

LOGO

PCB

Texas Instruments

NA
A

PCB Number:

PCB Rev:

Size: 0.65" x 0.20 "

PCB Label

LBL1

THT-14-423-10

CE Mark

LOGO

PCB

FCC disclaimer

LOGO

PCB

WEEE logo

1

H1

NY PMS 440 0025 PH

1

H2

NY PMS 440 0025 PH

1

H3

NY PMS 440 0025 PH

1

H4

NY PMS 440 0025 PH

H5

1902C

H6

1902C

H7

1902C

H8

1902C

FID2

DNP

FID1

DNP

FID3

DNP

Figure 5-3. TPS7H5001-SP Schematic (Page 3)

www.ti.com

Schematics

SLVUBZ8 – JULY 2021

Submit Document Feedback

TPS7H5001-SP Evaluation Module

11

Copyright © 2021 Texas Instruments Incorporated

Summary of Contents for TPS7H5001-SP

Page 1: ...ure 2 2 TPS7H5001 SP Output 4 Figure 2 3 Duty Cycle Generation 4 Figure 4 1 Top Overlay 7 Figure 4 2 Top Solder 7 Figure 4 3 Top Layer 7 Figure 4 4 Bottom Layer 7 Figure 4 5 Bottom Solder 8 Figure 4 6...

Page 2: ...the TPS7H5001 SP without additional hardware Minor changes were made to the BOM for manufacturability purposes 1 1 Features This EVM has the following features Synchronous rectification outputs with a...

Page 3: ...V input at 10 mA See Positive and Negative Terminal for J11 for connections TP9 COMP 1 V at 10 mA Input range can be 0 3 V to 3 3 V based on the TPS7H5001 SP Radiation Hardness Assured Si and GaN Dua...

Page 4: ...on the input voltage on COMP as well as the triangle waveform created by the CS_LIM circuit or any other waveform that the user decides to add to the CS_LIM pin See Duty Cycle Generation for signal g...

Page 5: ...7H5001 SP forcing this voltage runs the TPS7H5001 SP in open loop TP10 REFCAP Internal reference for TPS7H5001 SP TP11 TP12 SS In a closed loop design this slowly increases converter output voltage du...

Page 6: ...n Table 3 2 J6 Connections and Configuration Pin Connection Duty Cycle Limit Configuration Description Pin 1 and Pin 2 100 DCL is connected high to VLDO Pin 2 and Pin 3 50 DCL is connected low to AVSS...

Page 7: ...e EVM PCB layout images Figure 4 1 Top Overlay Figure 4 2 Top Solder Figure 4 3 Top Layer Figure 4 4 Bottom Layer www ti com PCB Layouts SLVUBZ8 JULY 2021 Submit Document Feedback TPS7H5001 SP Evaluat...

Page 8: ...Figure 4 6 Bottom Overlay Figure 4 7 Drill Drawing Figure 4 8 Board Dimensions PCB Layouts www ti com 8 TPS7H5001 SP Evaluation Module SLVUBZ8 JULY 2021 Submit Document Feedback Copyright 2021 Texas...

Page 9: ...GND OUTB 1 2 3 4 5 J3 AGND 1 2 3 4 5 J4 AGND SRA SRB OUTA TP1 EN TP8 SRA TP3 OUTB TP2 SRB TP4 20pF C5 1 00M R5 D DN N N N N NP 1 00M 1 00M R5 R5 AGND OUTA OUTB 20pF C6 1 00M R6 D DN N N N N N NP 1 00M...

Page 10: ...XIe 5172 1_CH3_Site1 PXIe 5172 1_CH5_Site1 PXIe 5172 1_CH7_Site1 PXIe 5172 1_CH0_Site1 PXIe 5172 1_CH2_Site1 PXIe 5172 1_CH4_Site1 PXIe 5172 1_CH6_Site1 PXIe 5172 General Purpose Up to 100MHz HICC FAU...

Page 11: ...172 2_CH3_Site1 PXIe 5172 2_CH5_Site1 PXIe 5172 2_CH7_Site1 DMM_Site1_4 DMM_Site1_5 AWG_CH2_to_SIte1 PXIe 5172 1_CH0_Site1 PXIe 5172 1_CH2_Site1 PXIe 5172 1_CH4_Site1 PXIe 5172 1_CH6_Site1 PXIe 5172 2...

Page 12: ...C28 C36 4 1uF CAP CERM 1 uF 50 V 10 X7R 0805 0805 885012207103 Wurth Elektronik C22 C25 C29 C37 4 1000pF CAP CERM 1000 pF 50 V 10 X7R 0805 0805 C0805C102K5RACTU Kemet C30 1 100uF CAP Tantalum Polymer...

Page 13: ...Ltd R31 1 135k RES 135 k 0 1 0 125 W 0805 0805 RT0805BRD07135KL Yageo America R33 1 191k RES 191 k 1 0 125 W AEC Q200 Grade 0 0805 0805 CRCW0805191KFKEA Vishay Dale R35 1 1 00Meg RES 1 00 M 0 5 0 1 W...

Page 14: ...0 0805 0805 08055A102KAT2A AVX C12 0 0 01uF CAP CERM 0 01 uF 50 V 20 X7R 0805 0805 C0805C103M5RACTU Kemet C13 0 0 47uF CAP CERM 0 47 uF 50 V 10 X7R AEC Q200 Grade 1 0805 0805 GCM21BR71H474KA55L MuRata...

Page 15: ...ther than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control tec...

Page 16: ...These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not in...

Page 17: ...instructions set forth by Radio Law of Japan which includes but is not limited to the instructions below with respect to EVMs which for the avoidance of doubt are stated strictly for convenience and s...

Page 18: ...any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electr...

Page 19: ...R DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthe...

Page 20: ...are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and...

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