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3 Detailed Descriptions

This section describes the connectors and the test points on the EVM and how to properly connect, set up and
use the TPS7H4010EVM. See 

Figure 1-2

 for a top view of the EVM. The "_x" in the table below refers

collectively to the the two converter circuits on the PCB: "POL_A" and "POL_B".

VOUT_A (J1 or
J20+) VOUT_B
(J10 or J22+)

Output voltage of the converter.

VOUT_x banana jack and terminal block connectors connect to the power inductor and the
output capacitors. Connect the loading device between VOUT_x and GND_x connectors to
provide loading to the converter. Connect the loading device to the board with short and
thick wires to handle the large DC output current.

GND_A (J2 or
J20-) GND_B (J11
or J22-)

Ground of the converter.

It is connected to the PGND and AGND of the device, as well as the input and output
capacitors. GND_x is the current return path for both supply voltage and load. Connect to
supply and load grounds with short and thick wires.

PVIN_A (J3 or
J19+) PVIN_B
(J12 or J21+)

Input voltage to the converter.

PVIN_x connectors and test points connect to the input capacitors and the PVIN pins of the
TPS7H4010-SEP. Connect the supply voltage from a power supply or a battery between
PVIN_x and GND_x connectors as power input to the board. The voltage range should be
higher than 3.5 V for the device to be active. PVIN should be no higher than 30 V to avoid
damaging the device. The current limit on the supply should be high enough to provide the
needed supply current, otherwise, the power supply will not maintain the desired voltage.
The supply voltage should be connected to the board with short and thick wires to handle
the pulsing input current. If long cables are used to power up the board, the damping
capacitors C14 and C32, located on the bottom side of board, should be added to avoid
oscillations between the cable parasitic inductance and the low-ESR ceramic capacitors.

PVIN_EMI_A (J4)
PVIN_EMI_B
(J13)

Input voltage to input filter of the converter (not installed by default)

If the input filter is desired between the supply voltage and the TPS7H4010-SEP, connect
the supply voltage between PVIN_EMI_x and GND_x. The supply voltage should be
connected to the board with short and thick wires to handle pulsing input current.

GND_A (J5)
GND_B (J14)

Ground connection near the input filter

This is the current return path for the supply connected to PVIN_EMI_x. It provides a direct
connection to the input filter capacitors to best filter the conducted noises generated from
the PCB. Use PVIN_EMI_x and GND_x connection if input filter is used and conducted EMI
test is desired.

POLA_Input Filter
(C11, C12, C13,
C14, L2)
POLB_Input Filter
(C29, C30, C31,
C32, L4)

Reduces noise from supply voltage

The input filter consists of a C-L-C pi configuration, located on the bottom side of the PCB.
To include the input filter in the power path, connect the supply voltage between the
PVIN_EMI_x and GND_x connectors. The output of the filter is connected to the PVIN net,
which is connected to the PVIN pins of the TPS7H4010-SEP and the input capacitors. Note
that the input filter components are not mounted on the PCB by default.

Conducted EMI arises from the normal operation of switching circuits. The ON and OFF
actions of the power switches generate large discontinuous currents. The discontinuous
currents are present at the input side of buck converters. Voltage ripple generated by
discontinuous currents can be conducted to the voltage supply of the buck converter via
physical contact of the conductors. Without control, excessive input voltage ripple can

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Detailed Descriptions

SNVU744 – OCTOBER 2020

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TPS7H4010EVM User's Guide

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Copyright © 2020 Texas Instruments Incorporated

Summary of Contents for TPS7H4010EVM

Page 1: ...7H4010 SEP Schematic 4 Figure 1 4 TPS7H4010 SEP Package Marking 5 Figure 4 1 TPS7H4010EVM PVIN 5 V VOUT 1 8 V Schematic 10 Figure 4 2 TPS7H4010EVM PVIN 12 V VOUT 3 3 V Schematic 11 Figure 5 1 Top Laye...

Page 2: ...ble 1 1 Device and Package Configurations 3 Table 1 2 Converter Circuit Variants 4 Table 6 1 TPS7H4010EVM BOM 17 Trademarks All other trademarks are the property of their respective owners Trademarks...

Page 3: ...figurations CONVERTER IC PACKAGE U1 U2 TPS7H4010 SEP 30 pin wettable flanks QFN WQFN 6 mm 4 mm 0 8 mm 1 2 TPS7H4010 SEP Synchronous Step Down Voltage Converter The TPS7H4010 SEP is an easy to use sync...

Page 4: ...The TPS7H4010 SEP evaluation module is orderable part number TPS7H4010EVM The EVM contains two independent converter circuits targeting two common applications POLA FSW 500 kHz PVIN 5 V VOUT 1 8 V IOU...

Page 5: ...Figure 1 4 TPS7H4010 SEP Package Marking www ti com Introduction SNVU744 OCTOBER 2020 Submit Document Feedback TPS7H4010EVM User s Guide 5 Copyright 2020 Texas Instruments Incorporated...

Page 6: ...e are being tested 1 Connect the input voltage supply between J3 PVIN_A and J2 GND_A using short low gauge wires Note For very accurate PVIN control across all load conditions connect sense lines from...

Page 7: ...d on the bottom side of board should be added to avoid oscillations between the cable parasitic inductance and the low ESR ceramic capacitors PVIN_EMI_A J4 PVIN_EMI_B J13 Input voltage to input filter...

Page 8: ...be found by Equation 2 Remove RENB from the board if it is desired to have the same voltage on the EN pin as the EN_EXT_x voltage schematic is shown in Figure 1 3 PGOOD_A TP11 PGOOD_B TP25 Test point...

Page 9: ...ternal clock SYNC_A TP13 SYNC_B TP27 Test point to monitor the SYNC MODE pin and external clock input The SYNC_x test point can used to monitor the SYNC MODE pin voltage on the device It is also the e...

Page 10: ...ematic is shown in Figure 4 1 below Figure 4 1 TPS7H4010EVM PVIN 5 V VOUT 1 8 V Schematic Schematic www ti com 10 TPS7H4010EVM User s Guide SNVU744 OCTOBER 2020 Submit Document Feedback Copyright 2020...

Page 11: ...Figure 4 2 TPS7H4010EVM PVIN 12 V VOUT 3 3 V Schematic www ti com Schematic SNVU744 OCTOBER 2020 Submit Document Feedback TPS7H4010EVM User s Guide 11 Copyright 2020 Texas Instruments Incorporated...

Page 12: ...optimal thermal performance The PCB consists of a 4 layer design There are 2 oz copper planes on the top and bottom and 1 oz copper mid layer planes to dissipate heat with an array of thermal vias und...

Page 13: ...Figure 5 2 Top Layer Routing www ti com Board Layout SNVU744 OCTOBER 2020 Submit Document Feedback TPS7H4010EVM User s Guide 13 Copyright 2020 Texas Instruments Incorporated...

Page 14: ...Figure 5 3 Mid Layer 1 Ground Plane Board Layout www ti com 14 TPS7H4010EVM User s Guide SNVU744 OCTOBER 2020 Submit Document Feedback Copyright 2020 Texas Instruments Incorporated...

Page 15: ...Figure 5 4 Mid Layer 2 Routing www ti com Board Layout SNVU744 OCTOBER 2020 Submit Document Feedback TPS7H4010EVM User s Guide 15 Copyright 2020 Texas Instruments Incorporated...

Page 16: ...Figure 5 5 Bottom Layer Routing Board Layout www ti com 16 TPS7H4010EVM User s Guide SNVU744 OCTOBER 2020 Submit Document Feedback Copyright 2020 Texas Instruments Incorporated...

Page 17: ...hine Screw Round 4 40 x 1 4 Nylon Philips panhead Screw NY PMS 440 0025 PH B F Fastener Supply H7 H8 H9 H10 H11 H12 6 Standoff Hex 0 5 L 4 40 Nylon Standoff 1902C Keystone J1 J2 J3 J4 J5 J10 J11 J12 J...

Page 18: ...5 2 TE Connectivity TP1 TP15 2 Test Point Multipurpose Orange TH Orange Multipurpose Testpoint 5013 Keystone TP2 TP3 TP7 TP8 TP9 TP10 TP16 TP17 TP21 TP22 TP23 TP24 12 Test Point Multipurpose Black TH...

Page 19: ...00 1 820 5 000 4 000 1 821 5 000 3 000 1 822 5 000 2 000 1 822 5 000 1 000 1 823 5 000 0 900 1 823 5 000 0 800 1 823 5 000 0 700 1 822 5 000 0 600 1 823 5 000 0 500 1 827 5 000 0 400 1 833 5 000 0 300...

Page 20: ...nse Figure 7 3 PVIN 5 V VOUT 1 8 V FSW 500 kHz Transient Response to current step from 2 A to 6 A at 1 A us TPS7H4010EVM Test Data www ti com 20 TPS7H4010EVM User s Guide SNVU744 OCTOBER 2020 Submit D...

Page 21: ...urrent step from 6 A to 2 A at 1 A us Figure 7 5 PVIN 5 V VOUT 1 8 V IOUT 6 A FSW 500 kHz Output Voltage Ripple www ti com TPS7H4010EVM Test Data SNVU744 OCTOBER 2020 Submit Document Feedback TPS7H401...

Page 22: ...IOUT 6 A FSW 500 kHz Soft Start Figure 7 7 FSW 500 kHz Efficiency vs IOUT TPS7H4010EVM Test Data www ti com 22 TPS7H4010EVM User s Guide SNVU744 OCTOBER 2020 Submit Document Feedback Copyright 2020 T...

Page 23: ...000 4 000 3 326 5 000 3 000 3 328 5 000 2 000 3 328 5 000 1 000 3 329 5 000 0 900 3 329 5 000 0 800 3 329 5 000 0 700 3 329 5 000 0 600 3 329 5 000 0 500 3 334 5 000 0 400 3 345 5 000 0 300 3 351 5 00...

Page 24: ...sponse Figure 7 10 PVIN 12 V VOUT 3 3 V FSW 500 kHz Transient Response to current step from 2 A to 6 A at 1 A us TPS7H4010EVM Test Data www ti com 24 TPS7H4010EVM User s Guide SNVU744 OCTOBER 2020 Sub...

Page 25: ...urrent step from 6 A to 2 A at 1 A us Figure 7 12 PVIN 12 V VOUT 3 3 V IOUT 6 A FSW 500 kHz Output Voltage Ripple www ti com TPS7H4010EVM Test Data SNVU744 OCTOBER 2020 Submit Document Feedback TPS7H4...

Page 26: ...V IOUT 6 A FSW 500 kHz Soft Start Figure 7 14 FSW 500 kHz Efficiency vs IOUT TPS7H4010EVM Test Data www ti com 26 TPS7H4010EVM User s Guide SNVU744 OCTOBER 2020 Submit Document Feedback Copyright 2020...

Page 27: ...ther than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control tec...

Page 28: ...These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not in...

Page 29: ...instructions set forth by Radio Law of Japan which includes but is not limited to the instructions below with respect to EVMs which for the avoidance of doubt are stated strictly for convenience and s...

Page 30: ...any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electr...

Page 31: ...R DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthe...

Page 32: ...e resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reprod...

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